Lines Matching +full:composite +full:- +full:divider +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI Divider Clock
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
16 #include "clock.h"
26 for (clkt = table; clkt->div; clkt++) in _get_table_div()
27 if (clkt->val == val) in _get_table_div()
28 return clkt->div; in _get_table_div()
32 static void _setup_mask(struct clk_omap_divider *divider) in _setup_mask() argument
38 if (divider->table) { in _setup_mask()
41 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
42 if (clkt->val > max_val) in _setup_mask()
43 max_val = clkt->val; in _setup_mask()
45 max_val = divider->max; in _setup_mask()
47 if (!(divider->flags & CLK_DIVIDER_ONE_BASED) && in _setup_mask()
48 !(divider->flags & CLK_DIVIDER_POWER_OF_TWO)) in _setup_mask()
49 max_val--; in _setup_mask()
52 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in _setup_mask()
53 mask = fls(max_val) - 1; in _setup_mask()
57 divider->mask = (1 << fls(mask)) - 1; in _setup_mask()
60 static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val) in _get_div() argument
62 if (divider->flags & CLK_DIVIDER_ONE_BASED) in _get_div()
64 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in _get_div()
66 if (divider->table) in _get_div()
67 return _get_table_div(divider->table, val); in _get_div()
76 for (clkt = table; clkt->div; clkt++) in _get_table_val()
77 if (clkt->div == div) in _get_table_val()
78 return clkt->val; in _get_table_val()
82 static unsigned int _get_val(struct clk_omap_divider *divider, u8 div) in _get_val() argument
84 if (divider->flags & CLK_DIVIDER_ONE_BASED) in _get_val()
86 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in _get_val()
88 if (divider->table) in _get_val()
89 return _get_table_val(divider->table, div); in _get_val()
90 return div - 1; in _get_val()
96 struct clk_omap_divider *divider = to_clk_omap_divider(hw); in ti_clk_divider_recalc_rate() local
99 val = ti_clk_ll_ops->clk_readl(÷r->reg) >> divider->shift; in ti_clk_divider_recalc_rate()
100 val &= divider->mask; in ti_clk_divider_recalc_rate()
102 div = _get_div(divider, val); in ti_clk_divider_recalc_rate()
104 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), in ti_clk_divider_recalc_rate()
117 #define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
124 for (clkt = table; clkt->div; clkt++) in _is_valid_table_div()
125 if (clkt->div == div) in _is_valid_table_div()
130 static bool _is_valid_div(struct clk_omap_divider *divider, unsigned int div) in _is_valid_div() argument
132 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in _is_valid_div()
134 if (divider->table) in _is_valid_div()
135 return _is_valid_table_div(divider->table, div); in _is_valid_div()
146 for (clkt = table; clkt->div; clkt++) { in _div_round_up()
147 if (clkt->div == div) in _div_round_up()
148 return clkt->div; in _div_round_up()
149 else if (clkt->div < div) in _div_round_up()
152 if ((clkt->div - div) < (up - div)) in _div_round_up()
153 up = clkt->div; in _div_round_up()
171 struct clk_omap_divider *divider = to_clk_omap_divider(hw); in ti_clk_divider_bestdiv() local
179 maxdiv = divider->max; in ti_clk_divider_bestdiv()
183 bestdiv = _div_round(divider->table, parent_rate, rate); in ti_clk_divider_bestdiv()
190 * The maximum divider we can use without overflowing in ti_clk_divider_bestdiv()
196 if (!_is_valid_div(divider, i)) in ti_clk_divider_bestdiv()
201 * divided from parent clock without needing to change in ti_clk_divider_bestdiv()
202 * parent rate, so return the divider immediately. in ti_clk_divider_bestdiv()
218 bestdiv = divider->max; in ti_clk_divider_bestdiv()
238 struct clk_omap_divider *divider; in ti_clk_divider_set_rate() local
243 return -EINVAL; in ti_clk_divider_set_rate()
245 divider = to_clk_omap_divider(hw); in ti_clk_divider_set_rate()
249 if (div > divider->max) in ti_clk_divider_set_rate()
250 div = divider->max; in ti_clk_divider_set_rate()
251 if (div < divider->min) in ti_clk_divider_set_rate()
252 div = divider->min; in ti_clk_divider_set_rate()
254 value = _get_val(divider, div); in ti_clk_divider_set_rate()
256 val = ti_clk_ll_ops->clk_readl(÷r->reg); in ti_clk_divider_set_rate()
257 val &= ~(divider->mask << divider->shift); in ti_clk_divider_set_rate()
258 val |= value << divider->shift; in ti_clk_divider_set_rate()
259 ti_clk_ll_ops->clk_writel(val, ÷r->reg); in ti_clk_divider_set_rate()
261 ti_clk_latch(÷r->reg, divider->latch); in ti_clk_divider_set_rate()
267 * clk_divider_save_context - Save the divider value
270 * Save the divider value
274 struct clk_omap_divider *divider = to_clk_omap_divider(hw); in clk_divider_save_context() local
277 val = ti_clk_ll_ops->clk_readl(÷r->reg) >> divider->shift; in clk_divider_save_context()
278 divider->context = val & divider->mask; in clk_divider_save_context()
284 * clk_divider_restore_context - restore the saved the divider value
287 * Restore the saved the divider value
291 struct clk_omap_divider *divider = to_clk_omap_divider(hw); in clk_divider_restore_context() local
294 val = ti_clk_ll_ops->clk_readl(÷r->reg); in clk_divider_restore_context()
295 val &= ~(divider->mask << divider->shift); in clk_divider_restore_context()
296 val |= divider->context << divider->shift; in clk_divider_restore_context()
297 ti_clk_ll_ops->clk_writel(val, ÷r->reg); in clk_divider_restore_context()
325 div->hw.init = &init; in _register_divider()
327 /* register the clock */ in _register_divider()
328 return of_ti_clk_register(node, &div->hw, name); in _register_divider()
332 u8 flags, struct clk_omap_divider *divider) in ti_clk_parse_divider_data() argument
340 divider->min = 1; in ti_clk_parse_divider_data()
341 divider->max = max_div; in ti_clk_parse_divider_data()
342 _setup_mask(divider); in ti_clk_parse_divider_data()
349 if (div_table[i] == -1) in ti_clk_parse_divider_data()
360 return -ENOMEM; in ti_clk_parse_divider_data()
375 divider->min = min_div; in ti_clk_parse_divider_data()
376 divider->max = max_div; in ti_clk_parse_divider_data()
377 divider->table = tmp; in ti_clk_parse_divider_data()
378 _setup_mask(divider); in ti_clk_parse_divider_data()
402 /* Determine required size for divider table */ in ti_clk_get_div_table()
411 return -EINVAL; in ti_clk_get_div_table()
416 return -ENOMEM; in ti_clk_get_div_table()
429 div->table = table; in ti_clk_get_div_table()
435 struct clk_omap_divider *divider) in _populate_divider_min_max() argument
442 if (!divider->table) { in _populate_divider_min_max()
443 /* Clk divider table not provided, determine min/max divs */ in _populate_divider_min_max()
444 if (of_property_read_u32(node, "ti,min-div", &min_div)) in _populate_divider_min_max()
447 if (of_property_read_u32(node, "ti,max-div", &max_div)) { in _populate_divider_min_max()
448 pr_err("no max-div for %pOFn!\n", node); in _populate_divider_min_max()
449 return -EINVAL; in _populate_divider_min_max()
453 for (clkt = divider->table; clkt->div; clkt++) { in _populate_divider_min_max()
454 val = clkt->div; in _populate_divider_min_max()
462 divider->min = min_div; in _populate_divider_min_max()
463 divider->max = max_div; in _populate_divider_min_max()
464 _setup_mask(divider); in _populate_divider_min_max()
476 ret = ti_clk_get_reg_addr(node, 0, &div->reg); in ti_clk_divider_populate()
480 div->shift = div->reg.bit; in ti_clk_divider_populate()
482 if (!of_property_read_u32(node, "ti,latch-bit", &val)) in ti_clk_divider_populate()
483 div->latch = val; in ti_clk_divider_populate()
485 div->latch = -EINVAL; in ti_clk_divider_populate()
488 div->flags = 0; in ti_clk_divider_populate()
490 if (of_property_read_bool(node, "ti,index-starts-at-one")) in ti_clk_divider_populate()
491 div->flags |= CLK_DIVIDER_ONE_BASED; in ti_clk_divider_populate()
493 if (of_property_read_bool(node, "ti,index-power-of-two")) in ti_clk_divider_populate()
494 div->flags |= CLK_DIVIDER_POWER_OF_TWO; in ti_clk_divider_populate()
496 if (of_property_read_bool(node, "ti,set-rate-parent")) in ti_clk_divider_populate()
507 * of_ti_divider_clk_setup - Setup function for simple div rate clock
508 * @node: device node for this clock
510 * Sets up a basic divider clock.
533 kfree(div->table); in of_ti_divider_clk_setup()
536 CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
550 if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER)) in of_ti_composite_divider_clk_setup()
554 kfree(div->table); in of_ti_composite_divider_clk_setup()
557 CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock",