Lines Matching +full:composite +full:- +full:divider +full:- +full:clock

1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,divider-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments divider clock
10   - Tero Kristo <kristo@kernel.org>
13   This clock It assumes a register-mapped adjustable clock rate divider
14   that does not gate and has only one input clock or parent.  By default the
25   ti,index-starts-at-one - valid divisor values start at 1, not the default
32   ti,index-power-of-two - valid divisor values are powers of two.  E.g:
49   Any zero value in this array means the corresponding bit-value is invalid
52   The binding must also provide the register to control the divider and
53   unless the divider array is provided, min and max dividers. Optionally
60   [1] Documentation/devicetree/bindings/clock/ti/autoidle.txt
65       - ti,divider-clock
66       - ti,composite-divider-clock
68   "#clock-cells":
74   clock-output-names:
81     $ref: /schemas/types.yaml#/definitions/uint32-array
85   ti,bit-shift:
88       number of bits to shift the divider value
92   ti,min-div:
95       min divisor for dividing the input clock rate, only
101   ti,max-div:
104       max divisor for dividing the input clock rate, only needed
107   ti,index-starts-at-one:
113   ti,index-power-of-two:
119   ti,autoidle-shift:
122       bit shift of the autoidle enable bit for the clock,
127   ti,invert-autoidle-bit:
133   ti,set-rate-parent:
138   ti,latch-bit:
141       latch the divider value to HW, only needed if the register
143       H14 divider implements such behavior.
148       ti,min-div: false
149       ti,max-div: false
150       ti,index-power-of-two: false
151       ti,index-starts-at-one: false
154   - compatible
155   - "#clock-cells"
156   - clocks
157   - reg
162   - |
164       #address-cells = <1>;
165       #size-cells = <0>;
167       clock-controller@190 {
168         #clock-cells = <0>;
169         compatible = "ti,divider-clock";
171         ti,max-div = <127>;
173         ti,index-starts-at-one;
176       clock-controller@528 {
177         #clock-cells = <0>;
178         compatible = "ti,divider-clock";
180         ti,bit-shift = <24>;
182         ti,max-div = <2>;
185       clock-controller@a40 {
186         #clock-cells = <0>;
187         compatible = "ti,composite-divider-clock";
189         ti,bit-shift = <8>;