| /freebsd/sys/contrib/device-tree/Bindings/mtd/ |
| H A D | ti,elm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments Error Location Module (ELM).
10 - Roger Quadros <rogerq@kernel.org>
13 ELM module is used together with GPMC and NAND Flash to detect
14 errors and the location of the error based on BCH algorithms
20 - ti,am3352-elm
21 - ti,am64-elm
31 description: Functional clock.
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| H A D | atmel-nand.txt | 4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
19 - #address-cells: should be set to 2.
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| /freebsd/sys/contrib/alpine-hal/eth/ |
| H A D | al_hal_eth_mac_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
410 /* [0x38] Signal detect configuration */
434 /* [0x68] Clock configuration */
473 /* [0x8] PCS clock divider configuration */
480 /* [0x0] Receive rate matching error */
488 * FEC corrected error indication
493 * FEC corrected error indication
498 * FEC corrected error indication
503 * FEC corrected error indication
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| H A D | al_hal_eth.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
61 /* *INDENT-OFF* */
65 /* *INDENT-ON* */
97 #define AL_ETH_TSO_MSS_MAX_VAL (AL_ETH_MAX_FRAME_LEN - 200)
194 * will be set according to inner packet when packet is tunneled, for non-tunneled
327 uint8_t l4_header_len; /**< in words(32-bits) */
342 * Target-ID to be assigned to the packet descriptors
343 * Requires Target-ID in descriptor to be enabled for the specific UDMA
356 /* Packet Rx flags - word 3 in Rx completion descriptor */
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| /freebsd/sys/contrib/device-tree/Bindings/rng/ |
| H A D | st,stm32-rng.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rng/st,stm32-rng.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Lionel Debieve <lionel.debieve@foss.st.com>
19 - st,stm32-rng
20 - st,stm32mp13-rng
31 clock-error-detect:
33 description: If set enable the clock detection management
35 st,rng-lock-conf:
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| /freebsd/sys/dev/mii/ |
| H A D | ciphyreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
156 #define CIPHY_1000STS_IEC 0x00FF /* Idle error count */
159 #define CIPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
160 #define CIPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
161 #define CIPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
162 #define CIPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
171 /* Vendor-specific PHY registers */
176 #define CIPHY_100STS_LKCERR 0x4000 /* lock error detected/lock lost */
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| H A D | nsphyterreg.h | 3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
45 #define PHYSTS_REL 0x8000 /* receive error latch */
53 #define PHYSTS_JABBER 0x0040 /* jabber detect */
61 #define PHYSTS_MP_REL 0x2000 /* receive error latch */
64 #define PHYSTS_MP_SIGNAL 0x0400 /* signal detect */
65 #define PHYSTS_MP_DESCRLK 0x0200 /* de-scrambler lock */
69 #define PHYSTS_MP_JABBER 0x0020 /* jabber detect */
85 #define MIPGSR_MSK_ANC 0x0800 /* mask auto-neg complete event */
87 #define MIPGSR_MSK_RHF 0x0200 /* mask RX error half full event */
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| /freebsd/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | renesas,mmcif.txt | 9 - compatible: should be "renesas,mmcif-<soctype>", "renesas,sh-mmcif" as a
11 - "renesas,mmcif-r7s72100" for the MMCIF found in r7s72100 SoCs
12 - "renesas,mmcif-r8a73a4" for the MMCIF found in r8a73a4 SoCs
13 - "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs
14 - "renesas,mmcif-r8a7742" for the MMCIF found in r8a7742 SoCs
15 - "renesas,mmcif-r8a7743" for the MMCIF found in r8a7743 SoCs
16 - "renesas,mmcif-r8a7744" for the MMCIF found in r8a7744 SoCs
17 - "renesas,mmcif-r8a7745" for the MMCIF found in r8a7745 SoCs
18 - "renesas,mmcif-r8a7778" for the MMCIF found in r8a7778 SoCs
19 - "renesas,mmcif-r8a7790" for the MMCIF found in r8a7790 SoCs
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_serdes_internal_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
48 * 0 - Hard reset is asserted
49 * 1 - Hard reset is de-asserted
58 * 0 - Hard reset is taken from the interface pins
59 * 1 - Hard reset is taken from registers
121 * PMA serial RX-to-TX loop-back enable (from AGC to IO Driver). Serial receive
122 * to transmit loopback: 0 - Disables loopback 1 - Transmits the untimed,
129 * PMA TX-to-RX buffered serial loop-back enable (bypasses IO Driver). Serial
130 * transmit to receive buffered loopback: 0 - Disables loopback 1 - Loops back
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| H A D | al_hal_serdes_hssp_internal_regs.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
47 * 0 - Hard reset is asserted
48 * 1 - Hard reset is de-asserted
57 * 0 - Hard reset is taken from the interface pins
58 * 1 - Hard reset is taken from registers
120 * PMA serial RX-to-TX loop-back enable (from AGC to IO Driver). Serial receive
121 * to transmit loopback: 0 - Disables loopback 1 - Transmits the untimed,
128 * PMA TX-to-RX buffered serial loop-back enable (bypasses IO Driver). Serial
129 * transmit to receive buffered loopback: 0 - Disables loopback 1 - Loops back
136 * PMA TX-to-RX I/O serial loop-back enable (loop back done directly from TX to
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| /freebsd/contrib/ntp/html/ |
| H A D | rdebug.html | 1 <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
5 <title>Debugging Reference Clock Drivers</title>
9 <h3>Debugging Reference Clock Drivers</h3>
13 <!-- #BeginDate format:En2m -->10-Mar-2014 05:19<!-- #EndDate -->
20 …clock appears in the <tt>ntpq</tt> utility and <tt>pe</tt> command, no errors have occurred and th…
21 …clock is running and the driver is operating correctly. The first indication is a nonzero value in…
22 …clock, the variables of interest can be inspected using the <tt>ntpq</tt> program and various comm…
23 …clock, as well as other peers of interest. The <tt>clockvar</tt> command with argument shows the p…
24 …clock driver status. The most useful are the <tt>clockstat</tt> and <tt>clkbug</tt> commands descr…
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| H A D | release.html | 1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
14 <!-- #BeginDate format:En1m -->3-Oc
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| /freebsd/sys/dev/ic/ |
| H A D | cd1400.h | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * cyclades cyclom-y serial driver
84 #define CD1400_RDSR_PE (1<<2) /* rx parity error */
85 #define CD1400_RDSR_FE (1<<1) /* rx framing error */
86 #define CD1400_RDSR_OE (1<<0) /* rx overrun error */
108 #define CD1400_CCR_SC (7<<0) /* special char 1-4 */
135 #define CD1400_COR2_IXOFF (1<<6) /* in-band tx flow control */
147 #define CD1400_COR3_SCDRNG (1<<7) /* special char detect range */
148 #define CD1400_COR3_SCD34 (1<<6) /* special char detect 3-4 */
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| /freebsd/sys/dev/uart/ |
| H A D | uart_dev_mvebu.c | 1 /*-
45 #define RBR_BRK_DET (1 << 15) /* Break Detect */
46 #define RBR_FRM_ERR_DET (1 << 14) /* Frame Error Detect */
47 #define RBR_PAR_ERR_DET (1 << 13) /* Parity Error Detect */
48 #define RBR_OVR_ERR_DET (1 << 12) /* Overrun Error */
61 #define CTRL_TX_HALF_INT (1 << 8) /* TX Half-Full Interrupt Enable */
62 #define CTRL_RX_HALF_INT (1 << 7) /* RX Half-Full Interrupt Enable */
66 #define CTRL_BRK_DET_INT (1 << 3) /* Break Detect Interrupt Enable */
67 #define CTRL_FRM_ERR_INT (1 << 2) /* Frame Error Interrupt Enable */
68 #define CTRL_PAR_ERR_INT (1 << 1) /* Parity Error Interrupt Enable */
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| /freebsd/sys/dev/le/ |
| H A D | lancereg.h | 3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
34 /*-
70 * - Am7990 Local Area Network Controller for Ethernet (LANCE)
71 * (and its descendent Am79c90 C-LANCE).
73 * - Am79c900 Integrated Local Area Communications Controller (ILACC)
75 * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA
77 * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
80 * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip
83 * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller
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| /freebsd/sys/dev/mmc/host/ |
| H A D | dwmmc_reg.h | 1 /*-
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
43 #define SDMMC_CLKDIV 0x8 /* Clock Divider Register */
44 #define SDMMC_CLKSRC 0xC /* SD Clock Source Register */
45 #define SDMMC_CLKENA 0x10 /* Clock Enable Register */
46 #define SDMMC_CLKENA_LP (1 << 16) /* Low-power mode */
56 #define SDMMC_INTMASK_EBE (1 << 15) /* End-bit error */
58 #define SDMMC_INTMASK_SBE (1 << 13) /* Start-bit error */
64 #define SDMMC_INTMASK_DCRC (1 << 7) /* Data CRC error */
65 #define SDMMC_INTMASK_RCRC (1 << 6) /* Response CRC error */
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| /freebsd/sys/dev/msk/ |
| H A D | if_mskreg.h | 17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
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| /freebsd/sys/contrib/device-tree/src/arm/samsung/ |
| H A D | exynos5410-odroidxu.dts | 1 // SPDX-License-Identifier: GPL-2.0
10 /dts-v1/;
12 #include <dt-bindings/clock/maxim,max77802.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/sound/samsung-i2s.h>
16 #include "exynos54xx-odroidxu-leds.dtsi"
20 compatible = "hardkernel,odroid-xu", "samsung,exynos5410", "samsung,exynos5";
34 stdout-path = "serial2:115200n8";
38 pinctrl-0 = <&emmc_nrst_pin>;
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| /freebsd/sys/dev/gem/ |
| H A D | if_gemreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
40 /* Note: Reading the status reg clears bits 0-6. */
69 * Bits 0-6 auto-clear when read.
77 #define GEM_INTR_PERR 0x00000080 /* Parity error */
78 #define GEM_INTR_PCS 0x00002000 /* Physical Code Sub-layer */
83 #define GEM_INTR_BERR 0x00040000 /* Bus error interrupt */
91 #define GEM_PCI_ERROR_STATUS 0x1000 /* PCI error status */
92 #define GEM_PCI_ERROR_MASK 0x1004 /* PCI error mask */
98 /* GEM_PCI_ERROR_STATUS and GEM_PCI_ERROR_MASK error bits */
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| /freebsd/contrib/ntp/ntpd/ |
| H A D | refclock_hopfser.c | 4 * - clock driver for hopf serial boards (GPS or DCF77)
50 * clock definitions
52 #define DESCRIPTION "hopf Elektronik serial clock" /* Long name */
53 #define PRECISION (-10) /* precision assumed (about 1 ms) */
73 #define HOPF_INTERNAL 0x04 /* internal clock */
74 #define HOPF_RADIO 0x08 /* radio clock */
75 #define HOPF_RADIOHP 0x0C /* high precision radio clock */
83 u_long polled; /* flag to detect noreplies */
111 * hopfserial_start - ope
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| /freebsd/share/doc/smm/12.timed/ |
| H A D | timed.ms | 45 Command under contract No. N00039-84-C-0089, and by the Italian CSELT
53 .OH 'The Berkeley UNIX Time Synchronization Protocol''SMM:12-%'
54 .EH 'SMM:12-%''The Berkeley UNIX Time Synchronization Protocol'
60 a local area network clock synchronizer for
77 (one per machine) and is based on a master-slave
82 difference between the clock of the machine on which it
84 uses ICMP \fITime Stamp Requests\fP [5] to measure the clock difference
89 A clock is considered to be faulty when its value
96 correction that should be performed on the clock of its machine.
102 will ask the master for the correct time and will reset the machine's clock
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| /freebsd/sys/dev/igc/ |
| H A D | igc_defines.h | 1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
92 #define IGC_RXD_ERR_CE 0x01 /* CRC Error */
93 #define IGC_RXD_ERR_SE 0x02 /* Symbol Error */
94 #define IGC_RXD_ERR_SEQ 0x04 /* Sequence Error */
95 #define IGC_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
96 #define IGC_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
97 #define IGC_RXD_ERR_IPE 0x40 /* IP Checksum Error */
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| /freebsd/contrib/ntp/sntp/libevent/ |
| H A D | whatsnew-2.1.txt | 27 There is a work-in-progress book with reference manual at
28 http://www.wangafu.net/~nickm/libevent-book/ .
31 on the mailing list at libevent-users@freehaven.net. The mailing list
32 is subscribers-only, so you will need to subscribe before you post.
36 Our source-compatibility policy is that correct code (that is to say,
44 probably need to be recompiled against Libevent 2.1.4-alpha if you
52 We now provide an --enable-gcc-hardening configure option to turn on
55 There is also an --enable-silent-rules configure option to make
58 You no longer need to use the --enable-gcc-warnings option to turn on
66 There is now an alternative cmake-based build process; cmake users
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| /freebsd/contrib/libevent/ |
| H A D | whatsnew-2.1.txt | 27 There is a work-in-progress book with reference manual at
28 http://www.wangafu.net/~nickm/libevent-book/ .
31 on the mailing list at libevent-users@freehaven.net. The mailing list
32 is subscribers-only, so you will need to subscribe before you post.
36 Our source-compatibility policy is that correct code (that is to say,
44 probably need to be recompiled against Libevent 2.1.4-alpha if you
52 We now provide an --enable-gcc-hardening configure option to turn on
55 There is also an --enable-silent-rules configure option to make
58 You no longer need to use the --enable-gcc-warnings option to turn on
66 There is now an alternative cmake-based build process; cmake users
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| /freebsd/sys/dev/iicbus/controller/rockchip/ |
| H A D | rk_i2c.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
143 {"rockchip,rk3288-i2c", 1},
144 {"rockchip,rk3328-i2c", 1},
145 {"rockchip,rk3399-i2c", 1},
152 { -1, 0 }
159 #define RK_I2C_LOCK(sc) mtx_lock(&(sc)->mtx)
160 #define RK_I2C_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
161 #define RK_I2C_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
162 #define RK_I2C_READ(sc, reg) bus_read_4((sc)->res[0], (reg))
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