Lines Matching +full:clock +full:- +full:error +full:- +full:detect
3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
34 /*-
70 * - Am7990 Local Area Network Controller for Ethernet (LANCE)
71 * (and its descendent Am79c90 C-LANCE).
73 * - Am79c900 Integrated Local Area Communications Controller (ILACC)
75 * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA
77 * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
80 * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip
83 * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller
86 * - Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI
89 * - Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller
92 * - Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps
95 * - Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller
98 * - Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI
101 * - Am79c978 PCnet-Home Single-Chip 1/10 Mbps PCI Home
107 * 16-bit software model (LANCE) am7990reg.h
109 * 32-bit software model (ILACC) am79900reg.h
112 * belong to follow-on chips to the original LANCE. Only CSR0-CSR3 are
122 #define LEMINSIZE (ETHER_MIN_LEN - ETHER_CRC_LEN)
124 #define LE_INITADDR(sc) (sc->sc_initaddr)
125 #define LE_RMDADDR(sc, bix) (sc->sc_rmdaddr + sizeof(struct lermd) * (bix))
126 #define LE_TMDADDR(sc, bix) (sc->sc_tmdaddr + sizeof(struct letmd) * (bix))
127 #define LE_RBUFADDR(sc, bix) (sc->sc_rbufaddr + LEBLEN * (bix))
128 #define LE_TBUFADDR(sc, bix) (sc->sc_tbufaddr + LEBLEN * (bix))
229 #define LE_BCR9 0x0009 /* Full-duplex Control */
265 #define LE_C0_ERR 0x8000 /* error summary */
266 #define LE_C0_BABL 0x4000 /* transmitter timeout error */
269 #define LE_C0_MERR 0x0800 /* memory error */
289 #define LE_C3_MERRM 0x0800 /* memory error mask */
303 #define LE_C4_DMAPLUS 0x4000 /* always set (PCnet-PCI) */
343 #define LE_C7_MREINT 0x0200 /* PHY management read error intr */
344 #define LE_C7_MREINTE 0x0100 /* PHY management read error intr
346 #define LE_C7_MAPINT 0x0080 /* PHY management auto-poll intr */
347 #define LE_C7_MAPINTE 0x0040 /* PHY management auto-poll intr
357 #define LE_C7_MIIPDTINT 0x0002 /* PHY management detect transition
359 #define LE_C7_MIIPDTINTE 0x0001 /* PHY management detect transition
367 #define LE_C15_DAPC 0x0800 /* disable auto-polarity correction */
413 #define LE_C125_IPG 0xff00 /* inter-packet gap */
414 #define LE_C125_IFS1 0x00ff /* inter-frame spacing part 1 */
431 #define LE_B2_ASEL 0x0002 /* auto-select PORTSEL */
444 #define LE_B4_FDLSE 0x0100 /* full-duplex link status enable */
455 #define LE_B9_FDRPAD 0x0004 /* full-duplex runt packet accept
457 #define LE_B9_AUIFD 0x0002 /* AUI full-duplex */
458 #define LE_B9_FDEN 0x0001 /* full-duplex enable */
465 #define LE_B18_DWIO 0x0080 /* double-word I/O */
479 #define LE_B19_EEDET 0x2000 /* EEPROM detect */
482 #define LE_B19_ESK 0x0002 /* EEPROM serial clock */
487 #define LE_B20_APERREN 0x0400 /* Advanced parity error handling */
488 #define LE_B20_CSRPCNET 0x0200 /* PCnet-style CSRs (0 = ILACC) */
489 #define LE_B20_SSIZE32 0x0100 /* Software Size 32-bit */
491 #define LE_B20_SSTYLE_LANCE 0 /* LANCE/PCnet-ISA (16-bit) */
492 #define LE_B20_SSTYLE_ILACC 1 /* ILACC (32-bit) */
493 #define LE_B20_SSTYLE_PCNETPCI2 2 /* PCnet-PCI (32-bit) */
494 #define LE_B20_SSTYLE_PCNETPCI3 3 /* PCnet-PCI II (32-bit) */
505 #define LE_B27_EBCS 0x0038 /* expansion bus clock source */
507 /* 001 time base clock */
511 #define LE_B27_CLK_FAC 0x0007 /* clock factor */
534 #define LE_B32_MIIPD 0x4000 /* MII PHY Detect (manuf. tests) */
535 #define LE_B32_FMDC 0x3000 /* fast management data clock */
536 #define LE_B32_APEP 0x0800 /* auto-poll PHY */
537 #define LE_B32_APDW 0x0700 /* auto-poll dwell time */
541 #define LE_B32_XPHYFD 0x0010 /* PHY full-duplex */
550 #define LE_B33_FDX 0x0800 /* full-duplex */
560 #define LE_B49_PCNET 0x8000 /* PCnet mode - Must Be One */
572 /* 0x4000 - 0x0080 are not available on LANCE 7990. */