Lines Matching +full:clock +full:- +full:error +full:- +full:detect
1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
92 #define IGC_RXD_ERR_CE 0x01 /* CRC Error */
93 #define IGC_RXD_ERR_SE 0x02 /* Symbol Error */
94 #define IGC_RXD_ERR_SEQ 0x04 /* Sequence Error */
95 #define IGC_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
96 #define IGC_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
97 #define IGC_RXD_ERR_IPE 0x40 /* IP Checksum Error */
98 #define IGC_RXD_ERR_RXE 0x80 /* Rx Data Error */
127 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
128 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
214 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
216 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
278 /* 1000/H is not supported, nor spec-compliant. */
328 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
345 /* GPY211 - I225 defines */
426 /* Uncorrectable/correctable ECC Error counts and enable bits */
449 #define IGC_ICR_RXSEQ 0x00000008 /* Rx sequence error */
459 #define IGC_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */
465 #define IGC_ICR_FER 0x00400000 /* Fatal Error */
491 * o RXSEQ = Receive Sequence Error
504 #define IGC_IMS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */
506 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
511 #define IGC_IMS_ECCER IGC_ICR_ECCER /* Uncorrectable ECC Error */
515 #define IGC_IMS_FER IGC_ICR_FER /* Fatal Error */
518 #define IGC_IMS_MDDET IGC_ICR_MDDET /* Malicious Driver Detect */
533 #define IGC_ICS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */
584 /* Error Codes */
604 /* Loop limit on how long we wait for auto-negotiation to complete */
626 #define IGC_TXCW_ANE 0x80000000 /* Auto-neg enable */
645 #define IGC_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */
683 #define TSAUXC_EN_CLK0 (1 << 2) /* Enable Configurable Frequency Clock 0. */
684 #define TSAUXC_ST0 (1 << 4) /* Start Clock 0 Toggle on Target Time 0. */
685 #define TSAUXC_EN_CLK1 (1 << 5) /* Enable Configurable Frequency Clock 1. */
686 #define TSAUXC_ST1 (1 << 7) /* Start Clock 1 Toggle on Target Time 1. */
709 #define TS_SDP0_SEL_FC0 (2u << 6) /* Freq clock 0 is output on SDP0. */
710 #define TS_SDP0_SEL_FC1 (3u << 6) /* Freq clock 1 is output on SDP0. */
711 #define TS_SDP1_SEL_FC0 (2u << 9) /* Freq clock 0 is output on SDP1. */
712 #define TS_SDP1_SEL_FC1 (3u << 9) /* Freq clock 1 is output on SDP1. */
715 #define TS_SDP2_SEL_FC0 (2u << 12) /* Freq clock 0 is output on SDP2. */
716 #define TS_SDP2_SEL_FC1 (3u << 12) /* Freq clock 1 is output on SDP2. */
719 #define TS_SDP3_SEL_FC0 (2u << 15) /* Freq clock 0 is output on SDP3. */
720 #define TS_SDP3_SEL_FC1 (3u << 15) /* Freq clock 1 is output on SDP3. */
810 #define IGC_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */
836 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
880 /* 1000BASE-T Control Register */
896 /* 1000BASE-T Status Register */
919 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
920 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
932 #define IGC_EECD_SK 0x00000001 /* NVM Clock */
1030 /* NVM Commands - Microwire */
1037 /* NVM Commands - SPI */
1041 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1069 /* PCI/PCI-X/PCI-EX Config space */
1095 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1118 #define M88IGC_RX_ERR_CNTR 0x15 /* Receive Error Counter */
1128 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1139 * 1 = 50-80M
1140 * 2 = 80-110M
1141 * 3 = 110-140M
1170 * 15-5: page
1171 * 4-0: register offset
1189 /* Page 193 - Port Control Registers */
1194 /* Page 194 - KMRN Registers */
1208 #define IGC_N0_QUEUE -1
1230 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1259 /* Minimum time for 1000BASE-T where no data will be transmit following move out
1263 /* Minimum time for 100BASE-T where no data will be transmit following move out