Lines Matching +full:clock +full:- +full:error +full:- +full:detect
1 /*-
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
43 #define SDMMC_CLKDIV 0x8 /* Clock Divider Register */
44 #define SDMMC_CLKSRC 0xC /* SD Clock Source Register */
45 #define SDMMC_CLKENA 0x10 /* Clock Enable Register */
46 #define SDMMC_CLKENA_LP (1 << 16) /* Low-power mode */
56 #define SDMMC_INTMASK_EBE (1 << 15) /* End-bit error */
58 #define SDMMC_INTMASK_SBE (1 << 13) /* Start-bit error */
64 #define SDMMC_INTMASK_DCRC (1 << 7) /* Data CRC error */
65 #define SDMMC_INTMASK_RCRC (1 << 6) /* Response CRC error */
70 #define SDMMC_INTMASK_RE (1 << 1) /* Response error */
101 #define SDMMC_CDETECT 0x50 /* Card Detect Register */
104 #define SDMMC_TBBCNT 0x60 /* Transferred Host to BIU-FIFO Byte Count */
109 #define SDMMC_UHS_REG 0x74 /* UHS-1 Register */
122 #define SDMMC_IDINTEN_CES (1 << 5) /* Card Error Summary */
124 #define SDMMC_IDINTEN_FBE (1 << 2) /* Fatal Bus Error */
149 /* Platform-specific defines */