Lines Matching +full:clock +full:- +full:error +full:- +full:detect
1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
156 #define CIPHY_1000STS_IEC 0x00FF /* Idle error count */
159 #define CIPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
160 #define CIPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
161 #define CIPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
162 #define CIPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
171 /* Vendor-specific PHY registers */
176 #define CIPHY_100STS_LKCERR 0x4000 /* lock error detected/lock lost */
179 #define CIPHY_100STS_RXERR 0x0800 /* receive error detected */
180 #define CIPHY_100STS_TXERR 0x0400 /* transmit error detected */
181 #define CIPHY_100STS_SSDERR 0x0200 /* false carrier error detected */
182 #define CIPHY_100STS_ESDERR 0x0100 /* premature end of stream error */
187 #define CIPHY_1000STS2_LKCERR 0x4000 /* lock error detected/lock lost */
190 #define CIPHY_1000STS2_RXERR 0x0800 /* receive error detected */
191 #define CIPHY_1000STS2_TXERR 0x0400 /* transmit error detected */
192 #define CIPHY_1000STS2_SSDERR 0x0200 /* false carrier error detected */
193 #define CIPHY_1000STS2_ESDERR 0x0100 /* premature end of stream error */
195 #define CIPHY_1000STS2_BCM5400 0x0040 /* non-complient BCM5400 detected */
206 #define CIPHY_BYPASS_TXCLK 0x0100 /* enable transmit clock on LED4 pin */
207 #define CIPHY_BYPASS_BCM5400_F 0x0080 /* force BCM5400 detect */
208 #define CIPHY_BYPASS_BCM5400 0x0040 /* bypass BCM5400 detect */
211 #define CIPHY_BYPASS_PARALLEL 0x0008 /* parallel detect enable */
215 /* RX error count register */
221 /* Ddisconnect error counter */
227 #define CIPHY_10BTCSR_JABBER 0x4000 /* Disable jabber detect */
229 #define CIPHY_10BTCSR_SQE 0x1000 /* Disable signal quality error */
231 #define CIPHY_10BTCSR_EOFERR 0x0100 /* End of Frame error */
287 #define CIPHY_IMR_ANEGERR 0x0800 /* autoneg error event */
290 #define CIPHY_IMR_SYMERR 0x0100 /* symbol error event */
294 #define CIPHY_IMR_JABBER 0x0010 /* jabber detect event */
295 #define CIPHY_IMR_SSDERR 0x0008 /* false carrier detect event */
296 #define CIPHY_IMR_ESDERR 0x0004 /* parallel detect error event */
298 #define CIPHY_IMR_RXERR 0x0001 /* RX error event */
306 #define CIPHY_ISR_ANEGERR 0x0800 /* autoneg error event */
309 #define CIPHY_ISR_SYMERR 0x0100 /* symbol error event */
313 #define CIPHY_ISR_JABBER 0x0010 /* jabber detect event */
314 #define CIPHY_ISR_SSDERR 0x0008 /* false carrier detect event */
315 #define CIPHY_ISR_ESDERR 0x0004 /* parallel detect error event */
317 #define CIPHY_ISR_RXERR 0x0001 /* RX error event */
339 #define CIPHY_AUXCSR_XOVER 0x2000 /* MDI/MDI-X crossover indication */