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/linux/Documentation/devicetree/bindings/net/
H A Drealtek,rtl82xx.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
20 - ethernet-phy-id001c.c800
21 - ethernet-phy-id001c.c816
22 - ethernet-phy-id001c.c838
23 - ethernet-phy-id001c.c840
[all …]
/linux/include/linux/platform_data/
H A Dsi5351.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * enum si5351_pll_src - Si5351 pll clock source
22 * enum si5351_multisynth_src - Si5351 multisynth clock source
34 * enum si5351_clkout_src - Si5351 clock output clock source
36 * @SI5351_CLKOUT_SRC_MSYNTH_N: clkout N source clock is multisynth N
37 * @SI5351_CLKOUT_SRC_MSYNTH_0_4: clkout N source clock is multisynth 0 (N<4)
39 * @SI5351_CLKOUT_SRC_XTAL: clkout N source clock is XTAL
40 * @SI5351_CLKOUT_SRC_CLKIN: clkout N source clock is CLKIN (Si5351C only)
51 * enum si5351_drive_strength - Si5351 clock output drive strength
67 * enum si5351_disable_state - Si5351 clock output disable state
[all …]
/linux/drivers/clk/
H A Dclk-si5351.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * clk-si5351.c: Skyworks / Silicon Labs Si5351A/B/C I2C Clock Generator
6 * Rabeeh Khoury <rabeeh@solid-run.com>
10 * https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
12 * https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/application-notes/AN619.pdf
18 #include <linux/clk-provider.h>
31 #include "clk-si5351.h"
63 struct si5351_hw_data *clkout; member
88 ret = regmap_read(drvdata->regmap, reg, &val); in si5351_reg_read()
90 dev_err(&drvdata->client->dev, in si5351_reg_read()
[all …]
H A Dclk-lmk04832.c1 // SPDX-License-Identifier: GPL-2.0
3 * LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner
14 #include <linux/clk-provider.h>
22 /* 0x000 - 0x00d System Functions */
34 /* 0x100 - 0x137 Device Clock and SYSREF Clock Output Control */
75 /* 0x138 - 0x145 SYSREF, SYNC, and Device Config */
124 /* 0x146 - 0x14a CLKin Control */
134 /* 0x14b - 0x152 Holdover */
136 /* 0x153 - 0x15f PLL1 Configuration */
143 /* 0x160 - 0x16e PLL2 Configuration */
[all …]
H A Dclk-wm831x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2011-2 Wolfson Microelectronics PLC.
10 #include <linux/clk-provider.h>
30 return clkdata->xtal_ena; in wm831x_xtal_is_prepared()
39 if (clkdata->xtal_ena) in wm831x_xtal_recalc_rate()
70 struct wm831x *wm831x = clkdata->wm831x; in wm831x_fll_is_prepared()
75 dev_err(wm831x->dev, "Unable to read FLL_CONTROL_1: %d\n", in wm831x_fll_is_prepared()
87 struct wm831x *wm831x = clkdata->wm831x; in wm831x_fll_prepare()
93 dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret); in wm831x_fll_prepare()
95 /* wait 2-3 ms for new frequency taking effect */ in wm831x_fll_prepare()
[all …]
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi_pll.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\ in hdmi_pll_dump()
26 hdmi_read_reg(pll->base, r)) in hdmi_pll_dump()
42 unsigned long fint, clkdco, clkout; in hdmi_pll_compute() local
47 const struct dss_pll_hw *hw = pll->pll.hw; in hdmi_pll_compute()
49 clkin = clk_get_rate(pll->pll.clkin); in hdmi_pll_compute()
56 n = DIV_ROUND_UP(clkin, hw->fint_max); in hdmi_pll_compute()
60 min_dco = roundup(hw->clkdco_min, fint); in hdmi_pll_compute()
71 if (WARN_ON(target_clkdco - clkdco > fint)) in hdmi_pll_compute()
74 mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint); in hdmi_pll_compute()
[all …]
H A Ddss.h1 /* SPDX-License-Identifier: GPL-2.0-only */
59 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
105 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
106 * Type-B PLLs: clkout[0] refers to m2.
112 unsigned long clkout[DSS_PLL_MAX_HSDIVS]; member
124 void (*disable)(struct dss_pll *pll); member
266 /* dss-of */
489 void (*disable)(struct omap_overlay_manager *mgr); member
/linux/Documentation/devicetree/bindings/clock/
H A Dsilabs,si5351.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3
16 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
19 - Alvin Šipraga <alsi@bang-olufsen.dk>
24 - silabs,si5351a # Si5351A, 20-QFN package
25 - silabs,si5351a-msop # Si5351A, 10-MSOP package
26 - silabs,si5351b # Si5351B, 20-QFN package
27 - silabs,si5351c # Si5351C, 20-QFN package
[all …]
/linux/drivers/clk/renesas/
H A Dr9a06g032-clocks.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
24 #include <linux/soc/renesas/r9a06g032-sysctrl.h>
26 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
33 * struct regbit - describe one bit in a register
35 * expressed in units of 32-bit words (not bytes),
43 * Since registers are aligned on 32-bit boundaries, the
44 * offset will be specified in 32-bit words rather than bytes.
48 * offset from bytes to 32-bit words.
61 * struct r9a06g032_gate - clock-related control bits
[all …]
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
32 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_register()
33 if (!dss->plls[i]) { in dss_pll_register()
34 dss->plls[i] = pll; in dss_pll_register()
35 pll->dss = dss; in dss_pll_register()
40 return -EBUSY; in dss_pll_register()
45 struct dss_device *dss = pll->dss; in dss_pll_unregister()
48 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_unregister()
49 if (dss->plls[i] == pll) { in dss_pll_unregister()
[all …]
/linux/drivers/rtc/
H A Drtc-max31335.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/clk-provider.h>
187 #define clk_hw_to_max31335(_hw) container_of(_hw, struct max31335_data, clkout)
192 struct clk_hw clkout; member
230 ret = regmap_bulk_read(max31335->regmap, MAX31335_SECONDS, date, in max31335_read_time()
235 tm->tm_sec = bcd2bin(date[0] & 0x7f); in max31335_read_time()
236 tm->tm_min = bcd2bin(date[1] & 0x7f); in max31335_read_time()
237 tm->tm_hour = bcd2bin(date[2] & 0x3f); in max31335_read_time()
238 tm->tm_wday = bcd2bin(date[3] & 0x7) - 1; in max31335_read_time()
239 tm->tm_mday = bcd2bin(date[4] & 0x3f); in max31335_read_time()
[all …]
H A Drtc-ab-b5ze-s3.c1 // SPDX-License-Identifier: GPL-2.0+
3 * rtc-ab-b5ze-s3 - Driver for Abracon AB-RTCMC-32.768Khz-B5ZE-S3
10 * https://www.abracon.com/realtimeclock/AB-RTCMC-32.768kHz-B5ZE-S3-Application-Manual.pdf
12 * This work is based on ISL12057 driver (drivers/rtc/rtc-isl12057.c).
24 #define DRV_NAME "rtc-ab-b5ze-s3"
71 #define ABB5ZES3_REG_ALRM_MN 0x0A /* Alarm - minute register */
73 #define ABB5ZES3_REG_ALRM_HR 0x0B /* Alarm - hours register */
75 #define ABB5ZES3_REG_ALRM_DT 0x0C /* Alarm - date register */
77 #define ABB5ZES3_REG_ALRM_DW 0x0D /* Alarm - day of the week reg. */
90 #define ABB5ZES3_REG_TIM_CLK_COF2 BIT(5) /* Clkout Freq bit 2 */
[all …]
H A Drtc-pcf8563.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2005-06 Tower Technologies
7 * Maintainers: http://www.nslu2-linux.org/
11 * https://www.nxp.com/docs/en/data-sheet/PCF8563.pdf
15 #include <linux/clk-provider.h>
92 err = regmap_read(pcf8563->regmap, PCF8563_REG_ST2, &buf); in pcf8563_set_alarm_mode()
103 return regmap_write(pcf8563->regmap, PCF8563_REG_ST2, buf); in pcf8563_set_alarm_mode()
112 err = regmap_read(pcf8563->regmap, PCF8563_REG_ST2, &buf); in pcf8563_get_alarm_mode()
135 rtc_update_irq(pcf8563->rtc, 1, RTC_IRQF | RTC_AF); in pcf8563_irq()
145 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch.
[all …]
/linux/Documentation/devicetree/bindings/net/can/
H A Dnxp,sja1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - enum:
20 - renesas,r9a06g032-sja1000 # RZ/N1D
[all …]
/linux/drivers/clk/ti/
H A Dadpll.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/clk-provider.h>
183 err = of_property_read_string_index(d->np, in ti_adpll_clk_get_name()
184 "clock-output-names", in ti_adpll_clk_get_name()
190 name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s", in ti_adpll_clk_get_name()
191 d->pa, postfix); in ti_adpll_clk_get_name()
207 d->clocks[index].clk = clock; in ti_adpll_setup_clock()
208 d->clocks[index].unregister = unregister; in ti_adpll_setup_clock()
214 dev_warn(d->dev, "clock %s con_id lookup may fail\n", in ti_adpll_setup_clock()
216 snprintf(con_id, 16, "pll%03lx%s", d->pa & 0xfff, postfix + 1); in ti_adpll_setup_clock()
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnuvoton,npcm845-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nuvoton,npcm845-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tomer Maimon <tmaimon77@gmail.com>
13 The Nuvoton BMC NPCM8XX Pin Controller multi-function routed through
20 const: nuvoton,npcm845-pinctrl
25 '#address-cells':
28 '#size-cells':
44 gpio-controller: true
[all …]
H A Dnuvoton,npcm7xx-pinctrl.txt3 The Nuvoton BMC NPCM7XX Pin Controller multi-function routed through
9 - #address-cells : should be 1.
10 - #size-cells : should be 1.
11 - compatible : "nuvoton,npcm750-pinctrl" for Poleg NPCM7XX.
12 - ranges : defines mapping ranges between pin controller node (parent)
19 Required GPIO Bank subnode-properties:
20 - reg : specifies physical base address and size of the GPIO
22 - gpio-controller : Marks the device node as a GPIO controller.
23 - #gpio-cells : Must be <2>. The first cell is the gpio pin number
25 - interrupts : contain the GPIO bank interrupt with flags for falling edge.
[all …]
/linux/drivers/net/can/cc770/
H A Dcc770.c1 // SPDX-License-Identifier: GPL-2.0-only
44 * 2. Support of silent (listen-only) mode.
47 * Details are available from Bosch's "CC770_Product_Info_2007-01.pdf",
59 * "msgobj15_eff". If not equal 0, it will receive 29-bit EFF frames,
64 MODULE_PARM_DESC(msgobj15_eff, "Extended 29-bit frames for message object 15 "
65 "(default: 11-bit standard frames)");
103 return MSGOBJ_LAST + 2 - intid; in intid2obj()
113 for (o = 0; o < ARRAY_SIZE(priv->obj_flags); o++) { in enable_all_objs()
114 obj_flags = priv->obj_flags[o]; in enable_all_objs()
122 if (priv->control_normal_mode & CTRL_EAF) { in enable_all_objs()
[all …]
H A Dcc770.h1 /* SPDX-License-Identifier: GPL-2.0-only */
35 u8 clkout; /* Clock Out Register */ member
100 #define RXIE_RES 0x04 /* Receive Interrupt Disable */
103 #define TXIE_RES 0x10 /* Transmit Interrupt Disable */
141 priv->read_reg(priv, offsetof(struct cc770_regs, member))
144 priv->write_reg(priv, offsetof(struct cc770_regs, member), value)
162 #define obj2msgobj(o) (MSGOBJ_LAST - (o)) /* message object 11..15 */
171 /* the lower-layer is responsible for appropriate locking */
177 void *priv; /* for board-specific data */
186 u8 clkout; /* Clock out register */ member
/linux/arch/arm/boot/dts/nuvoton/
H A Dnuvoton-npcm750-pincfg-evb.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 pin8_input: pin8-input {
8 bias-disable;
9 input-enable;
11 pin9_output_high: pin9-output-high {
13 bias-disable;
14 output-high;
16 pin10_input: pin10-input {
18 bias-disable;
19 input-enable;
[all …]
H A Dnuvoton-npcm750-runbmc-olympus-pincfg.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 gpio0ol_pins: gpio0ol-pins {
8 bias-disable;
9 output-low;
11 gpio1ol_pins: gpio1ol-pins {
13 bias-disable;
14 output-low;
16 gpio2ol_pins: gpio2ol-pins {
18 bias-disable;
19 output-low;
[all …]
/linux/drivers/clk/ux500/
H A Dclk-prcmu.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 ST-Ericsson SA
9 #include <linux/clk-provider.h>
10 #include <linux/mfd/dbx500-prcmu.h>
38 return prcmu_request_clock(clk->cg_sel, true); in clk_prcmu_prepare()
44 if (prcmu_request_clock(clk->cg_sel, false)) in clk_prcmu_unprepare()
45 pr_err("clk_prcmu: %s failed to disable %s.\n", __func__, in clk_prcmu_unprepare()
53 return prcmu_clock_rate(clk->cg_sel); in clk_prcmu_recalc_rate()
60 return prcmu_round_clock_rate(clk->cg_sel, rate); in clk_prcmu_round_rate()
67 return prcmu_set_clock_rate(clk->cg_sel, rate); in clk_prcmu_set_rate()
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-debix-som-a-bmb-08.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "imx8mp-debix-som-a.dtsi"
12 model = "Polyhex i.MX8MPlus Debix SOM A on BMB-08";
13 compatible = "polyhex,imx8mp-debix-som-a-bmb-08", "polyhex,imx8mp-debix-som-a",
22 stdout-path = &uart2;
25 reg_baseboard_vdd3v3: regulator-baseboard-vdd3v3 {
26 compatible = "regulator-fixed";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
[all …]
/linux/sound/soc/codecs/
H A Dssm2602.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
75 #define APANA_ENABLE_SIDETONE 0x020 /* Enable/Disable Side Tone …
80 #define APDIGI_ENABLE_ADC_HPF 0x001 /* Enable/Disable ADC Highpass Filter …
81 #define APDIGI_DE_EMPHASIS 0x006 /* De-Emphasis Control …
86 *(1=Enable PowerDown, 0=Disable PowerDown)
94 #define PWR_CLK_OUT_PDN 0x040 /* CLKOUT Power Down …
102 #define IFACE_ENABLE_MASTER 0x040 /* Enable/Disable Master Mode …
106 #define SRATE_ENABLE_USB_MODE 0x001 /* Enable/Disable USB Mode …
107 #define SRATE_BOS_RATE 0x002 /* Base Over-Sampling rate …
/linux/arch/arm/boot/dts/st/
H A Dstm32mp135f-dhcor-dhsbc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG
7 * DHCOR PCB number: 718-100 or newer
8 * DHSBC PCB number: 719-100 or newer
11 /dts-v1/;
13 #include <dt-bindings/regulator/st,stm32mp13-regulator.h>
16 #include "stm32mp13xx-dhcor-som.dtsi"
20 compatible = "dh,stm32mp135f-dhcor-dhsbc",
21 "dh,stm32mp135f-dhcor-som",
32 stdout-path = "serial0:115200n8";
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