Lines Matching +full:clkout +full:- +full:disable
1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/clk-provider.h>
183 err = of_property_read_string_index(d->np, in ti_adpll_clk_get_name()
184 "clock-output-names", in ti_adpll_clk_get_name()
190 name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s", in ti_adpll_clk_get_name()
191 d->pa, postfix); in ti_adpll_clk_get_name()
207 d->clocks[index].clk = clock; in ti_adpll_setup_clock()
208 d->clocks[index].unregister = unregister; in ti_adpll_setup_clock()
214 dev_warn(d->dev, "clock %s con_id lookup may fail\n", in ti_adpll_setup_clock()
216 snprintf(con_id, 16, "pll%03lx%s", d->pa & 0xfff, postfix + 1); in ti_adpll_setup_clock()
219 return -ENOMEM; in ti_adpll_setup_clock()
220 d->clocks[index].cl = cl; in ti_adpll_setup_clock()
222 dev_warn(d->dev, "no con_id for clock %s\n", name); in ti_adpll_setup_clock()
228 d->outputs.clks[output_index] = clock; in ti_adpll_setup_clock()
229 d->outputs.clk_num++; in ti_adpll_setup_clock()
248 return -EINVAL; in ti_adpll_init_divider()
251 clock = clk_register_divider(d->dev, child_name, parent_name, 0, in ti_adpll_init_divider()
253 &d->lock); in ti_adpll_init_divider()
255 dev_err(d->dev, "failed to register divider %s: %li\n", in ti_adpll_init_divider()
275 child_name = ti_adpll_clk_get_name(d, -ENODEV, name); in ti_adpll_init_mux()
277 return -ENOMEM; in ti_adpll_init_mux()
280 clock = clk_register_mux(d->dev, child_name, parents, 2, 0, in ti_adpll_init_mux()
281 reg, shift, 1, 0, &d->lock); in ti_adpll_init_mux()
283 dev_err(d->dev, "failed to register mux %s: %li\n", in ti_adpll_init_mux()
288 return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name, in ti_adpll_init_mux()
306 return -EINVAL; in ti_adpll_init_gate()
309 clock = clk_register_gate(d->dev, child_name, parent_name, 0, in ti_adpll_init_gate()
311 &d->lock); in ti_adpll_init_gate()
313 dev_err(d->dev, "failed to register gate %s: %li\n", in ti_adpll_init_gate()
333 child_name = ti_adpll_clk_get_name(d, -ENODEV, name); in ti_adpll_init_fixed_factor()
335 return -ENOMEM; in ti_adpll_init_fixed_factor()
338 clock = clk_register_fixed_factor(d->dev, child_name, parent_name, in ti_adpll_init_fixed_factor()
343 return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name, in ti_adpll_init_fixed_factor()
352 spin_lock_irqsave(&d->lock, flags); in ti_adpll_set_idle_bypass()
353 v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET); in ti_adpll_set_idle_bypass()
355 writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET); in ti_adpll_set_idle_bypass()
356 spin_unlock_irqrestore(&d->lock, flags); in ti_adpll_set_idle_bypass()
364 spin_lock_irqsave(&d->lock, flags); in ti_adpll_clear_idle_bypass()
365 v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET); in ti_adpll_clear_idle_bypass()
367 writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET); in ti_adpll_clear_idle_bypass()
368 spin_unlock_irqrestore(&d->lock, flags); in ti_adpll_clear_idle_bypass()
375 v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET); in ti_adpll_clock_is_bypass()
382 * about the DCO clock and not CLKOUT you can clear M2PWDNZ before enabling
387 u32 v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET); in ti_adpll_is_locked()
400 } while (retries--); in ti_adpll_wait_lock()
402 dev_err(d->dev, "pll failed to lock\n"); in ti_adpll_wait_lock()
403 return -ETIMEDOUT; in ti_adpll_wait_lock()
449 spin_lock_irqsave(&d->lock, flags); in ti_adpll_recalc_rate()
450 frac_m = readl_relaxed(d->regs + ADPLL_FRACDIV_OFFSET); in ti_adpll_recalc_rate()
452 rate = (u64)readw_relaxed(d->regs + ADPLL_MN2DIV_OFFSET) << 18; in ti_adpll_recalc_rate()
455 divider = (readw_relaxed(d->regs + ADPLL_M2NDIV_OFFSET) + 1) << 18; in ti_adpll_recalc_rate()
456 spin_unlock_irqrestore(&d->lock, flags); in ti_adpll_recalc_rate()
460 if (d->c->is_type_s) { in ti_adpll_recalc_rate()
461 v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET); in ti_adpll_recalc_rate()
491 d->outputs.clks = devm_kcalloc(d->dev, in ti_adpll_init_dco()
495 if (!d->outputs.clks) in ti_adpll_init_dco()
496 return -ENOMEM; in ti_adpll_init_dco()
498 if (d->c->output_index < 0) in ti_adpll_init_dco()
503 init.name = ti_adpll_clk_get_name(d, d->c->output_index, postfix); in ti_adpll_init_dco()
505 return -EINVAL; in ti_adpll_init_dco()
507 init.parent_names = d->parent_names; in ti_adpll_init_dco()
508 init.num_parents = d->c->nr_max_inputs; in ti_adpll_init_dco()
511 d->dco.hw.init = &init; in ti_adpll_init_dco()
513 if (d->c->is_type_s) in ti_adpll_init_dco()
519 err = ti_adpll_init_divider(d, TI_ADPLL_N2, -ENODEV, "n2", in ti_adpll_init_dco()
520 d->parent_clocks[TI_ADPLL_CLKINP], in ti_adpll_init_dco()
521 d->regs + ADPLL_MN2DIV_OFFSET, in ti_adpll_init_dco()
526 clock = devm_clk_register(d->dev, &d->dco.hw); in ti_adpll_init_dco()
530 return ti_adpll_setup_clock(d, clock, TI_ADPLL_DCO, d->c->output_index, in ti_adpll_init_dco()
537 struct clk_hw *gate_hw = &co->gate.hw; in ti_adpll_clkout_enable()
547 struct clk_hw *gate_hw = &co->gate.hw; in ti_adpll_clkout_disable()
550 clk_gate_ops.disable(gate_hw); in ti_adpll_clkout_disable()
556 struct clk_hw *gate_hw = &co->gate.hw; in ti_adpll_clkout_is_enabled()
563 /* Setting PLL bypass puts clkout and clkoutx2 into bypass */
567 struct ti_adpll_data *d = co->adpll; in ti_adpll_clkout_get_parent()
586 co = devm_kzalloc(d->dev, sizeof(*co), GFP_KERNEL); in ti_adpll_init_clkout()
588 return -ENOMEM; in ti_adpll_init_clkout()
589 co->adpll = d; in ti_adpll_init_clkout()
591 err = of_property_read_string_index(d->np, in ti_adpll_init_clkout()
592 "clock-output-names", in ti_adpll_init_clkout()
598 ops = devm_kzalloc(d->dev, sizeof(*ops), GFP_KERNEL); in ti_adpll_init_clkout()
600 return -ENOMEM; in ti_adpll_init_clkout()
605 co->hw.init = &init; in ti_adpll_init_clkout()
611 ops->get_parent = ti_adpll_clkout_get_parent; in ti_adpll_init_clkout()
612 ops->determine_rate = __clk_mux_determine_rate; in ti_adpll_init_clkout()
614 co->gate.lock = &d->lock; in ti_adpll_init_clkout()
615 co->gate.reg = d->regs + ADPLL_CLKCTRL_OFFSET; in ti_adpll_init_clkout()
616 co->gate.bit_idx = gate_bit; in ti_adpll_init_clkout()
617 ops->enable = ti_adpll_clkout_enable; in ti_adpll_init_clkout()
618 ops->disable = ti_adpll_clkout_disable; in ti_adpll_init_clkout()
619 ops->is_enabled = ti_adpll_clkout_is_enabled; in ti_adpll_init_clkout()
622 clock = devm_clk_register(d->dev, &co->hw); in ti_adpll_init_clkout()
624 dev_err(d->dev, "failed to register output %s: %li\n", in ti_adpll_init_clkout()
637 if (!d->c->is_type_s) in ti_adpll_init_children_adpll_s()
642 d->clocks[TI_ADPLL_N2].clk, in ti_adpll_init_children_adpll_s()
643 d->parent_clocks[TI_ADPLL_CLKINPULOW], in ti_adpll_init_children_adpll_s()
644 d->regs + ADPLL_CLKCTRL_OFFSET, in ti_adpll_init_children_adpll_s()
650 err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV, "m2", in ti_adpll_init_children_adpll_s()
651 d->clocks[TI_ADPLL_DCO].clk, in ti_adpll_init_children_adpll_s()
652 d->regs + ADPLL_M2NDIV_OFFSET, in ti_adpll_init_children_adpll_s()
659 /* Internal fixed divider, after M2 before clkout */ in ti_adpll_init_children_adpll_s()
661 d->clocks[TI_ADPLL_M2].clk, in ti_adpll_init_children_adpll_s()
666 /* Output clkout with a mux and gate, sources from div2 or bypass */ in ti_adpll_init_children_adpll_s()
668 ADPLL_CLKCTRL_CLKOUTEN, "clkout", in ti_adpll_init_children_adpll_s()
669 d->clocks[TI_ADPLL_DIV2].clk, in ti_adpll_init_children_adpll_s()
670 d->clocks[TI_ADPLL_BYPASS].clk); in ti_adpll_init_children_adpll_s()
676 "clkout2", d->clocks[TI_ADPLL_M2].clk, in ti_adpll_init_children_adpll_s()
677 d->clocks[TI_ADPLL_BYPASS].clk); in ti_adpll_init_children_adpll_s()
682 if (d->parent_clocks[TI_ADPLL_CLKINPHIF]) { in ti_adpll_init_children_adpll_s()
684 d->clocks[TI_ADPLL_DCO].clk, in ti_adpll_init_children_adpll_s()
685 d->parent_clocks[TI_ADPLL_CLKINPHIF], in ti_adpll_init_children_adpll_s()
686 d->regs + ADPLL_CLKCTRL_OFFSET, in ti_adpll_init_children_adpll_s()
694 d->clocks[TI_ADPLL_HIF].clk, in ti_adpll_init_children_adpll_s()
695 d->regs + ADPLL_M3DIV_OFFSET, in ti_adpll_init_children_adpll_s()
711 if (d->c->is_type_s) in ti_adpll_init_children_adpll_lj()
716 "clkdcoldo", d->clocks[TI_ADPLL_DCO].clk, in ti_adpll_init_children_adpll_lj()
717 d->regs + ADPLL_CLKCTRL_OFFSET, in ti_adpll_init_children_adpll_lj()
723 err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV, in ti_adpll_init_children_adpll_lj()
724 "m2", d->clocks[TI_ADPLL_DCO].clk, in ti_adpll_init_children_adpll_lj()
725 d->regs + ADPLL_M2NDIV_OFFSET, in ti_adpll_init_children_adpll_lj()
734 "clkoutldo", d->clocks[TI_ADPLL_M2].clk, in ti_adpll_init_children_adpll_lj()
735 d->regs + ADPLL_CLKCTRL_OFFSET, in ti_adpll_init_children_adpll_lj()
743 d->clocks[TI_ADPLL_N2].clk, in ti_adpll_init_children_adpll_lj()
744 d->parent_clocks[TI_ADPLL_CLKINPULOW], in ti_adpll_init_children_adpll_lj()
745 d->regs + ADPLL_CLKCTRL_OFFSET, in ti_adpll_init_children_adpll_lj()
750 /* Output clkout, sources M2 or bypass */ in ti_adpll_init_children_adpll_lj()
752 ADPLL_CLKCTRL_CLKOUTEN, "clkout", in ti_adpll_init_children_adpll_lj()
753 d->clocks[TI_ADPLL_M2].clk, in ti_adpll_init_children_adpll_lj()
754 d->clocks[TI_ADPLL_BYPASS].clk); in ti_adpll_init_children_adpll_lj()
765 for (i = TI_ADPLL_M3; i >= 0; i--) { in ti_adpll_free_resources()
766 struct ti_adpll_clock *ac = &d->clocks[i]; in ti_adpll_free_resources()
768 if (!ac || IS_ERR_OR_NULL(ac->clk)) in ti_adpll_free_resources()
770 if (ac->cl) in ti_adpll_free_resources()
771 clkdev_drop(ac->cl); in ti_adpll_free_resources()
772 if (ac->unregister) in ti_adpll_free_resources()
773 ac->unregister(ac->clk); in ti_adpll_free_resources()
791 if (d->c->is_type_s) { in ti_adpll_init_registers()
793 ti_adpll_unlock_all(d->iobase + ADPLL_PLLSS_MMR_LOCK_OFFSET); in ti_adpll_init_registers()
796 d->regs = d->iobase + register_offset + ADPLL_PWRCTRL_OFFSET; in ti_adpll_init_registers()
807 nr_inputs = of_clk_get_parent_count(d->np); in ti_adpll_init_inputs()
808 if (nr_inputs < d->c->nr_max_inputs) { in ti_adpll_init_inputs()
809 dev_err(d->dev, error, nr_inputs); in ti_adpll_init_inputs()
810 return -EINVAL; in ti_adpll_init_inputs()
812 of_clk_parent_fill(d->np, d->parent_names, nr_inputs); in ti_adpll_init_inputs()
814 clock = devm_clk_get(d->dev, d->parent_names[0]); in ti_adpll_init_inputs()
816 dev_err(d->dev, "could not get clkinp\n"); in ti_adpll_init_inputs()
819 d->parent_clocks[TI_ADPLL_CLKINP] = clock; in ti_adpll_init_inputs()
821 clock = devm_clk_get(d->dev, d->parent_names[1]); in ti_adpll_init_inputs()
823 dev_err(d->dev, "could not get clkinpulow clock\n"); in ti_adpll_init_inputs()
826 d->parent_clocks[TI_ADPLL_CLKINPULOW] = clock; in ti_adpll_init_inputs()
828 if (d->c->is_type_s) { in ti_adpll_init_inputs()
829 clock = devm_clk_get(d->dev, d->parent_names[2]); in ti_adpll_init_inputs()
831 dev_err(d->dev, "could not get clkinphif clock\n"); in ti_adpll_init_inputs()
834 d->parent_clocks[TI_ADPLL_CLKINPHIF] = clock; in ti_adpll_init_inputs()
849 .nr_max_inputs = MAX_ADPLL_INPUTS - 1,
850 .nr_max_outputs = MAX_ADPLL_OUTPUTS - 1,
851 .output_index = -EINVAL,
855 { .compatible = "ti,dm814-adpll-s-clock", &ti_adpll_type_s },
856 { .compatible = "ti,dm814-adpll-lj-clock", &ti_adpll_type_lj },
863 struct device_node *node = pdev->dev.of_node; in ti_adpll_probe()
864 struct device *dev = &pdev->dev; in ti_adpll_probe()
871 return -ENOMEM; in ti_adpll_probe()
872 d->dev = dev; in ti_adpll_probe()
873 d->np = node; in ti_adpll_probe()
874 d->c = device_get_match_data(dev); in ti_adpll_probe()
875 dev_set_drvdata(d->dev, d); in ti_adpll_probe()
876 spin_lock_init(&d->lock); in ti_adpll_probe()
878 d->iobase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in ti_adpll_probe()
879 if (IS_ERR(d->iobase)) in ti_adpll_probe()
880 return PTR_ERR(d->iobase); in ti_adpll_probe()
881 d->pa = res->start; in ti_adpll_probe()
891 d->clocks = devm_kcalloc(d->dev, in ti_adpll_probe()
895 if (!d->clocks) in ti_adpll_probe()
896 return -ENOMEM; in ti_adpll_probe()
911 err = of_clk_add_provider(d->np, of_clk_src_onecell_get, &d->outputs); in ti_adpll_probe()
926 struct ti_adpll_data *d = dev_get_drvdata(&pdev->dev); in ti_adpll_remove()
933 .name = "ti-adpll",
953 MODULE_ALIAS("platform:dm814-adpll-clock");