Lines Matching +full:clkout +full:- +full:disable
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3
16 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
19 - Alvin Šipraga <alsi@bang-olufsen.dk>
24 - silabs,si5351a # Si5351A, 20-QFN package
25 - silabs,si5351a-msop # Si5351A, 10-MSOP package
26 - silabs,si5351b # Si5351B, 20-QFN package
27 - silabs,si5351c # Si5351C, 20-QFN package
31 - 0x60
32 - 0x61
34 "#address-cells":
37 "#size-cells":
40 "#clock-cells":
47 clock-names:
50 - const: xtal
51 - const: clkin
53 silabs,pll-source:
54 $ref: /schemas/types.yaml#/definitions/uint32-matrix
60 - description: PLL A (0) or PLL B (1)
62 - description: PLL source, XTAL (0) or CLKIN (1, Si5351C only).
65 silabs,pll-reset-mode:
66 $ref: /schemas/types.yaml#/definitions/uint32-matrix
72 - description: PLL A (0) or PLL B (1)
74 - description: |
77 0 - reset whenever PLL rate is adjusted (default mode)
78 1 - do not reset when PLL rate is adjusted
80 In mode 1, the PLL is only reset if the silabs,pll-reset is
87 "^clkout@[0-7]$":
96 clock-frequency: true
98 silabs,clock-source:
103 0 - use multisynth N for this output, where N is the output number
104 1 - use either multisynth 0 (if output number is 0-3) or multisynth 4
106 2 - use XTAL for this output
107 3 - use CLKIN for this output (Si5351C only)
109 silabs,drive-strength:
114 silabs,multisynth-source:
120 silabs,pll-master:
126 silabs,pll-reset:
130 silabs,disable-state:
134 Clock output disable state. The state can be one of:
136 0 - clock output is driven LOW when disabled
137 1 - clock output is driven HIGH when disabled
138 2 - clock output is FLOATING (HIGH-Z) when disabled
139 3 - clock output is never disabled
142 - if:
146 const: silabs,si5351a-msop
156 - if:
163 silabs,clock-source:
167 silabs,clock-source:
171 - reg
174 - if:
179 - silabs,si5351a
180 - silabs,si5351a-msop
181 - silabs,si5351b
186 clock-names:
190 - reg
191 - "#address-cells"
192 - "#size-cells"
193 - "#clock-cells"
194 - clocks
195 - clock-names
200 - |
202 #address-cells = <1>;
203 #size-cells = <0>;
205 clock-generator@60 {
206 compatible = "silabs,si5351a-msop";
208 #address-cells = <1>;
209 #size-cells = <0>;
210 #clock-cells = <1>;
214 clock-names = "xtal";
217 silabs,pll-source = <0 0>, <1 0>;
220 silabs,pll-reset-mode = <1 1>;
224 * - 8 mA output drive strength
225 * - PLL0 as clock source of multisynth 0
226 * - Multisynth 0 as clock source of output divider
227 * - Multisynth 0 can change PLL0
228 * - Set initial clock frequency of 74.25MHz
230 clkout@0 {
232 silabs,drive-strength = <8>;
233 silabs,multisynth-source = <0>;
234 silabs,clock-source = <0>;
235 silabs,pll-master;
236 clock-frequency = <74250000>;
241 * - 4 mA output drive strength
242 * - PLL1 as clock source of multisynth 1
243 * - Multisynth 1 as clock source of output divider
244 * - Multisynth 1 can change PLL1
245 * - Reset PLL1 when enabling this clock output
247 clkout@1 {
249 silabs,drive-strength = <4>;
250 silabs,multisynth-source = <1>;
251 silabs,clock-source = <0>;
252 silabs,pll-master;
253 silabs,pll-reset;
258 * - XTAL as clock source of output divider
260 clkout@2 {
262 silabs,clock-source = <2>;