1 // SPDX-License-Identifier: GPL-2.0-or-later
5  * Copyright 2011-2 Wolfson Microelectronics PLC.
10 #include <linux/clk-provider.h>
30 	return clkdata->xtal_ena;  in wm831x_xtal_is_prepared()
39 	if (clkdata->xtal_ena)  in wm831x_xtal_recalc_rate()
70 	struct wm831x *wm831x = clkdata->wm831x;  in wm831x_fll_is_prepared()
75 		dev_err(wm831x->dev, "Unable to read FLL_CONTROL_1: %d\n",  in wm831x_fll_is_prepared()
87 	struct wm831x *wm831x = clkdata->wm831x;  in wm831x_fll_prepare()
93 		dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret);  in wm831x_fll_prepare()
95 	/* wait 2-3 ms for new frequency taking effect */  in wm831x_fll_prepare()
105 	struct wm831x *wm831x = clkdata->wm831x;  in wm831x_fll_unprepare()
110 		dev_crit(wm831x->dev, "Failed to disable FLL: %d\n", ret);  in wm831x_fll_unprepare()
118 	struct wm831x *wm831x = clkdata->wm831x;  in wm831x_fll_recalc_rate()
123 		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",  in wm831x_fll_recalc_rate()
131 	dev_err(wm831x->dev, "FLL only supported in AUTO mode\n");  in wm831x_fll_recalc_rate()
143 		if (abs(wm831x_fll_auto_rates[i] - rate) <  in wm831x_fll_round_rate()
144 		    abs(wm831x_fll_auto_rates[best] - rate))  in wm831x_fll_round_rate()
155 	struct wm831x *wm831x = clkdata->wm831x;  in wm831x_fll_set_rate()
162 		return -EINVAL;  in wm831x_fll_set_rate()
165 		return -EPERM;  in wm831x_fll_set_rate()
180 	struct wm831x *wm831x = clkdata->wm831x;  in wm831x_fll_get_parent()
186 		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",  in wm831x_fll_get_parent()
196 		dev_err(wm831x->dev, "Unable to read FLL_CONTROL_5: %d\n",  in wm831x_fll_get_parent()
207 		dev_err(wm831x->dev, "Unsupported FLL clock source %d\n",  in wm831x_fll_get_parent()
235 	struct wm831x *wm831x = clkdata->wm831x;  in wm831x_clkout_is_prepared()
240 		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",  in wm831x_clkout_is_prepared()
252 	struct wm831x *wm831x = clkdata->wm831x;  in wm831x_clkout_prepare()
257 		dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);  in wm831x_clkout_prepare()
264 		dev_crit(wm831x->dev, "Failed to enable CLKOUT: %d\n", ret);  in wm831x_clkout_prepare()
275 	struct wm831x *wm831x = clkdata->wm831x;  in wm831x_clkout_unprepare()
280 		dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);  in wm831x_clkout_unprepare()
287 		dev_crit(wm831x->dev, "Failed to disable CLKOUT: %d\n", ret);  in wm831x_clkout_unprepare()
301 	struct wm831x *wm831x = clkdata->wm831x;  in wm831x_clkout_get_parent()
306 		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",  in wm831x_clkout_get_parent()
321 	struct wm831x *wm831x = clkdata->wm831x;  in wm831x_clkout_set_parent()
338 	.name = "clkout",
347 	struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);  in wm831x_clk_probe()
351 	clkdata = devm_kzalloc(&pdev->dev, sizeof(*clkdata), GFP_KERNEL);  in wm831x_clk_probe()
353 		return -ENOMEM;  in wm831x_clk_probe()
355 	clkdata->wm831x = wm831x;  in wm831x_clk_probe()
360 		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",  in wm831x_clk_probe()
364 	clkdata->xtal_ena = ret & WM831X_XTAL_ENA;  in wm831x_clk_probe()
366 	clkdata->xtal_hw.init = &wm831x_xtal_init;  in wm831x_clk_probe()
367 	ret = devm_clk_hw_register(&pdev->dev, &clkdata->xtal_hw);  in wm831x_clk_probe()
371 	clkdata->fll_hw.init = &wm831x_fll_init;  in wm831x_clk_probe()
372 	ret = devm_clk_hw_register(&pdev->dev, &clkdata->fll_hw);  in wm831x_clk_probe()
376 	clkdata->clkout_hw.init = &wm831x_clkout_init;  in wm831x_clk_probe()
377 	ret = devm_clk_hw_register(&pdev->dev, &clkdata->clkout_hw);  in wm831x_clk_probe()
389 		.name	= "wm831x-clk",
399 MODULE_ALIAS("platform:wm831x-clk");