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/linux/drivers/clk/nxp/
H A Dclk-lpc32xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/lpc32xx-clock.h>
165 static struct clk *clk[LPC32XX_CLK_MAX]; variable
167 .clks = clk,
171 static struct clk *usb_clk[LPC32XX_USB_CLK_MAX];
253 * divider register does not contain information about selected rate.
329 enum clk_pll_mode mode; member
378 static inline u32 lpc32xx_usb_clk_read(struct lpc32xx_usb_clk *clk) in lpc32xx_usb_clk_read() argument
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/linux/drivers/clk/davinci/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on arch/arm/mach-davinci/clock.c
8 * Copyright (C) 2006-2007 Texas Instruments.
9 * Copyright (C) 2008-2009 Deep Root Systems, LLC
12 #include <linux/clk-provider.h>
13 #include <linux/clk.h>
14 #include <linux/clk/davinci.h>
22 #include <linux/platform_data/clk-davinci-pll.h>
79 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
80 * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
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/linux/drivers/clk/
H A Dclk-cdce925.c5 * Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve
7 * deliver using the standard clk framework. In addition, the device can
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
54 u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */
73 struct clk_cdce925_output clk[MAX_NUMBER_OF_OUTPUTS]; member
82 return parent_rate; /* In bypass mode runs at same frequency */ in cdce925_pll_calculate_rate()
92 return cdce925_pll_calculate_rate(parent_rate, data->n, data->m); in cdce925_pll_recalc_rate()
103 /* Can always deliver parent_rate in bypass mode */ in cdce925_pll_find_rate()
107 /* In PLL mode, need to apply min/max range */ in cdce925_pll_find_rate()
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/linux/drivers/clk/zynqmp/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Xilinx
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
11 #include "clk-zynqmp.h"
14 * struct zynqmp_pll - PLL clock
15 * @hw: Handle between common and hardware-specific interfaces
44 * zynqmp_pll_get_mode() - Get mode of PLL
45 * @hw: Handle between common and hardware-specific interfaces
47 * Return: Mode of PLL
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/linux/drivers/gpu/ipu-v3/
H A Dipu-di.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
14 #include <video/imx-ipu-v3.h>
15 #include "ipu-prv.h"
21 struct clk *clk_di; /* display input clock */
22 struct clk *clk_ipu; /* IPU bus clock */
23 struct clk *clk_di_pixel; /* resulting pixel clock */
76 #define DI_SW_GEN0(gen) (0x000c + 4 * ((gen) - 1))
77 #define DI_SW_GEN1(gen) (0x0030 + 4 * ((gen) - 1))
78 #define DI_STP_REP(gen) (0x0148 + 4 * (((gen) - 1)/2))
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/linux/drivers/clk/ti/
H A Ddpll3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP3/4 - specific DPLL control functions
5 * Copyright (C) 2009-2010 Texas Instruments, Inc.
6 * Copyright (C) 2009-2010 Nokia Corporation
23 #include <linux/clk.h>
27 #include <linux/clk/ti.h>
40 static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
41 static void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
42 static void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
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H A Dclkt_dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2008 Texas Instruments, Inc.
6 * Copyright (C) 2004-2010 Nokia Corporation
9 * Richard Woodruff <r-woodruff2@ti.com>
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
19 #include <linux/clk/ti.h>
25 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
30 #define DPLL_MULT_UNDERFLOW -1
51 #define DPLL_FINT_UNDERFLOW -1
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H A Dfapll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/clk.h>
4 #include <linux/clk-provider.h>
11 #include <linux/clk/ti.h>
49 /* Synthesizer divider register */
63 struct clk *clk_ref;
64 struct clk *clk_bypass;
76 struct clk *clk_pll;
81 u32 v = readl_relaxed(fd->base); in ti_fapll_clock_is_bypass()
83 if (fd->bypass_bit_inverted) in ti_fapll_clock_is_bypass()
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/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
28 clock-names:
31 '#clock-cells':
34 clock-output-names:
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk20a.c2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
48 for (pl = 0; pl < ARRAY_SIZE(_pl_to_div) - 1; pl++) { in div_to_pl()
53 return ARRAY_SIZE(_pl_to_div) - 1; in div_to_pl()
65 gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll) in gk20a_pllg_read_mnp() argument
67 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_read_mnp()
71 pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); in gk20a_pllg_read_mnp()
72 pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); in gk20a_pllg_read_mnp()
73 pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); in gk20a_pllg_read_mnp()
77 gk20a_pllg_write_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll) in gk20a_pllg_write_mnp() argument
79 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_write_mnp()
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/linux/drivers/clk/renesas/
H A Drcar-gen3-cpg.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
23 CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
26 CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
27 CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
29 CLK_TYPE_GEN3_E3_RPCSRC,/* Select parent/divider using RPCCKCR.DIV */
82 struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
84 struct clk **clks, void __iomem *base,
87 unsigned int clk_extalr, u32 mode);
/linux/drivers/spi/
H A Dspi-meson-spicc.c7 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
29 * The PIO mode is the only mode implemented, and due to badly designed HW :
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * - CS management is dumb, and goes UP between every burst, so is really a
69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
89 #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */
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/linux/drivers/clk/meson/
H A Dclk-dualdiv.c1 // SPDX-License-Identifier: GPL-2.0
9 * The AO Domain embeds a dual/divider to generate a more precise
10 * 32,768KHz clock for low-power suspend mode and CEC.
13 * | Div1 |-| Cnt1 |
15 * -| ______ ______ X--> Out
17 * | Div2 |-| Cnt2 |
21 * for each divider to set when the switching is done.
24 #include <linux/clk-provider.h>
27 #include "clk-regmap.h"
28 #include "clk-dualdiv.h"
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/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_lvds.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car LVDS Encoder
5 * Copyright (C) 2013-2018 Renesas Electronics Corporation
10 #include <linux/clk.h>
13 #include <linux/media-bus-format.h>
54 #define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */
74 struct clk *mod; /* CPG module clock */
75 struct clk *extal; /* External clock */
76 struct clk *dotclkin[2]; /* External DU clocks */
88 return ioread32(lvds->mmio + reg); in rcar_lvds_read()
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/linux/drivers/phy/amlogic/
H A Dphy-meson-axg-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk.h>
33 * [11] mipi divider clk selection.
34 * 1: select the mipi DDRCLKHS from clock divider.
36 * [10] mipi clock divider control.
38 * [9] mipi divider output enable.
39 * [8] mipi divider counter enable.
44 * [3] force data byte lane in stop mode.
45 * [2] force data byte lane 0 in receiver mode.
52 /* [31] clk lane tx_hs_en control selection.
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/linux/include/linux/iio/frequency/
H A Dad9523.h1 /* SPDX-License-Identifier: GPL-2.0-only */
38 * struct ad9523_channel_spec - Output channel configuration
42 * @sync_ignore_en: Ignore chip-level SYNC signal.
44 * @use_alt_clock_src: Channel divider uses alternative clk source.
46 * @driver_mode: Output driver mode (logic level family).
47 * @divider_phase: Divider initial phase after a SYNC. Range 0..63
48 LSB = 1/2 of a period of the divider input clock.
49 * @channel_divider: 10-bit channel divider.
106 * struct ad9523_platform_data - platform specific information
109 * @refa_diff_rcv_en: REFA differential/single-ended input selection.
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/linux/include/linux/clk/
H A Dti.h1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include <linux/clk-provider.h>
14 * struct clk_omap_reg - OMAP register declaration
29 * struct dpll_data - DPLL registers and integration data
35 * @control_reg: register containing the DPLL mode bitfield
36 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
43 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
45 * @min_divider: minimum valid non-bypass divider value (actual)
46 * @max_divider: maximum valid non-bypass divider value (actual)
49 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
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/linux/drivers/cpufreq/
H A Darmada-37xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 #include <linux/clk.h>
24 #include "cpufreq-dt.h"
26 /* Clk register set */
69 * divider, a VDD level, etc...
100 u8 divider[LOAD_LEVEL_NR]; member
109 /* {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} }, */
110 {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
111 {.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} },
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/linux/sound/soc/stm/
H A Dstm32_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
136 #define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
137 I2S_CGFR_I2SDIV_SHIFT)) - 1)
198 #define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER)
199 #define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE)
208 * struct stm32_i2s_data - private data of I2S
223 * @lock_fd: lock to manage race conditions in full duplex mode
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/linux/drivers/mfd/
H A Dfsl-imx25-tsadc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2015 Pengutronix, Markus Pargmann <mpa@pengutronix.de>
6 #include <linux/clk.h>
12 #include <linux/mfd/imx25-tsadc.h>
35 regmap_read(tsadc->regs, MX25_TSC_TGSR, &status); in mx25_tsadc_irq_handler()
38 generic_handle_domain_irq(tsadc->domain, 1); in mx25_tsadc_irq_handler()
41 generic_handle_domain_irq(tsadc->domain, 0); in mx25_tsadc_irq_handler()
49 struct mx25_tsadc *tsadc = d->host_data; in mx25_tsadc_domain_map()
67 struct device *dev = &pdev->dev; in mx25_tsadc_setup_irq()
68 struct device_node *np = dev->of_node; in mx25_tsadc_setup_irq()
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/linux/drivers/clk/st/
H A Dclk-flexgen.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * clk-flexgen.c
5 * Copyright (C) ST-Microelectronics SA 2013
6 * Author: Maxime Coquelin <maxime.coquelin@st.com> for ST-Microelectronics.
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
26 bool mode; member
36 /* Pre-divisor's gate */
38 /* Pre-divisor */
44 /* Asynchronous mode control */
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/linux/drivers/gpu/drm/sprd/
H A Dsprd_dsi.h1 /* SPDX-License-Identifier: GPL-2.0 */
68 u8 refin; /* Pre-divider control signal */
70 u8 fdk_s; /* PLL mode control: integer or fraction */
81 u8 out_sel; /* post divider control */
102 /* maximum time (ns) for clk lanes from HS to LP */
104 /* maximum time (ns) for clk lanes from LP to HS */
106 /* maximum time (ns) for BTA operation - REQUIRED */
108 /* enable receiving frame ack packets - for video mode */
110 /* enable receiving tear effect ack packets - for cmd mode */
/linux/include/dt-bindings/clock/
H A Dtegra234-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
36 /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
52 * divided by the divider controlled by ACLK_CLK_DIVISOR in
56 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT switch divider output */
60 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB switch divider output */
62 /** @brief CLK_RST_CONTROLLER_AON_NIC_RATE divider output */
64 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC switch divider output */
81 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0 divider gated output */
83 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 divider gated output */
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-venice-gw7902.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-imx8-pcie.h>
18 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
29 stdout-path = &uart2;
38 compatible = "fixed-clock";
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/linux/drivers/clk/bcm/
H A Dclk-iproc-armpll.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
71 val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET); in __get_fid()
80 val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET); in __get_fid()
84 val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET); in __get_fid()
88 pr_debug("%s: fid override %u->%u\n", __func__, fid, in __get_fid()
99 * Determine the mdiv (post divider) based on the frequency ID being used.
101 * - 25 MHz Crystal
102 * - System clock
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