Lines Matching +full:clk +full:- +full:divider +full:- +full:mode
5 * Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve
7 * deliver using the standard clk framework. In addition, the device can
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
54 u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */
73 struct clk_cdce925_output clk[MAX_NUMBER_OF_OUTPUTS]; member
82 return parent_rate; /* In bypass mode runs at same frequency */ in cdce925_pll_calculate_rate()
92 return cdce925_pll_calculate_rate(parent_rate, data->n, data->m); in cdce925_pll_recalc_rate()
103 /* Can always deliver parent_rate in bypass mode */ in cdce925_pll_find_rate()
107 /* In PLL mode, need to apply min/max range */ in cdce925_pll_find_rate()
146 data->m = 0; /* Bypass mode */ in cdce925_pll_set_rate()
147 data->n = 0; in cdce925_pll_set_rate()
154 return -EINVAL; in cdce925_pll_set_rate()
160 return -EINVAL; in cdce925_pll_set_rate()
163 cdce925_pll_find_rate(rate, parent_rate, &data->n, &data->m); in cdce925_pll_set_rate()
168 /* calculate p = max(0, 4 - int(log2 (n/m))) */
179 --p; in cdce925_pll_calc_p()
187 struct clk *parent = clk_get_parent(hw->clk); in cdce925_pll_calc_range_bits()
205 u16 n = data->n; in cdce925_pll_prepare()
206 u16 m = data->m; in cdce925_pll_prepare()
212 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; in cdce925_pll_prepare()
216 /* Set PLL mux to bypass mode, leave the rest as is */ in cdce925_pll_prepare()
217 regmap_update_bits(data->chip->regmap, in cdce925_pll_prepare()
221 /* p = max(0, 4 - int(log2 (n/m))) */ in cdce925_pll_prepare()
229 return -EINVAL; in cdce925_pll_prepare()
231 r = nn - (m*q); in cdce925_pll_prepare()
234 return -EINVAL; in cdce925_pll_prepare()
246 regmap_write(data->chip->regmap, in cdce925_pll_prepare()
249 regmap_update_bits(data->chip->regmap, in cdce925_pll_prepare()
259 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; in cdce925_pll_unprepare()
261 regmap_update_bits(data->chip->regmap, in cdce925_pll_unprepare()
276 switch (data->index) { in cdce925_clk_set_pdiv()
278 regmap_update_bits(data->chip->regmap, in cdce925_clk_set_pdiv()
281 regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF); in cdce925_clk_set_pdiv()
284 regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv); in cdce925_clk_set_pdiv()
287 regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv); in cdce925_clk_set_pdiv()
290 regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv); in cdce925_clk_set_pdiv()
293 regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv); in cdce925_clk_set_pdiv()
296 regmap_update_bits(data->chip->regmap, 0x36, 0x7F, pdiv); in cdce925_clk_set_pdiv()
299 regmap_update_bits(data->chip->regmap, 0x37, 0x7F, pdiv); in cdce925_clk_set_pdiv()
302 regmap_update_bits(data->chip->regmap, 0x46, 0x7F, pdiv); in cdce925_clk_set_pdiv()
305 regmap_update_bits(data->chip->regmap, 0x47, 0x7F, pdiv); in cdce925_clk_set_pdiv()
312 switch (data->index) { in cdce925_clk_activate()
314 regmap_update_bits(data->chip->regmap, in cdce925_clk_activate()
319 regmap_update_bits(data->chip->regmap, 0x14, 0x03, 0x03); in cdce925_clk_activate()
323 regmap_update_bits(data->chip->regmap, 0x24, 0x03, 0x03); in cdce925_clk_activate()
327 regmap_update_bits(data->chip->regmap, 0x34, 0x03, 0x03); in cdce925_clk_activate()
331 regmap_update_bits(data->chip->regmap, 0x44, 0x03, 0x03); in cdce925_clk_activate()
340 cdce925_clk_set_pdiv(data, data->pdiv); in cdce925_clk_prepare()
349 /* Disable clock by setting divider to "0" */ in cdce925_clk_unprepare()
358 if (data->pdiv) in cdce925_clk_recalc_rate()
359 return parent_rate / data->pdiv; in cdce925_clk_recalc_rate()
366 unsigned long divider; in cdce925_calc_divider() local
373 divider = DIV_ROUND_CLOSEST(parent_rate, rate); in cdce925_calc_divider()
374 if (divider > 0x7F) in cdce925_calc_divider()
375 divider = 0x7F; in cdce925_calc_divider()
377 return (u16)divider; in cdce925_calc_divider()
383 struct clk *pll = clk_get_parent(hw->clk); in cdce925_clk_best_parent_rate()
384 struct clk *root = clk_get_parent(pll); in cdce925_clk_best_parent_rate()
411 rate_error = abs((long)actual_rate - (long)rate); in cdce925_clk_best_parent_rate()
427 u16 divider = cdce925_calc_divider(rate, l_parent_rate); in cdce925_clk_round_rate() local
429 if (l_parent_rate / divider != rate) { in cdce925_clk_round_rate()
431 divider = cdce925_calc_divider(rate, l_parent_rate); in cdce925_clk_round_rate()
435 if (divider) in cdce925_clk_round_rate()
436 return (long)(l_parent_rate / divider); in cdce925_clk_round_rate()
445 data->pdiv = cdce925_calc_divider(rate, parent_rate); in cdce925_clk_set_rate()
462 unsigned long divider; in cdce925_y1_calc_divider() local
469 divider = DIV_ROUND_CLOSEST(parent_rate, rate); in cdce925_y1_calc_divider()
470 if (divider > 0x3FF) /* Y1 has 10-bit divider */ in cdce925_y1_calc_divider()
471 divider = 0x3FF; in cdce925_y1_calc_divider()
473 return (u16)divider; in cdce925_y1_calc_divider()
480 u16 divider = cdce925_y1_calc_divider(rate, l_parent_rate); in cdce925_clk_y1_round_rate() local
482 if (divider) in cdce925_clk_y1_round_rate()
483 return (long)(l_parent_rate / divider); in cdce925_clk_y1_round_rate()
492 data->pdiv = cdce925_y1_calc_divider(rate, parent_rate); in cdce925_clk_y1_set_rate()
517 return -ENOTSUPP; in cdce925_regmap_i2c_write()
523 dev_dbg(&i2c->dev, "%s(%zu) %#x %#x\n", __func__, count, in cdce925_regmap_i2c_write()
532 return -EIO; in cdce925_regmap_i2c_write()
545 return -ENOTSUPP; in cdce925_regmap_i2c_read()
547 xfer[0].addr = i2c->addr; in cdce925_regmap_i2c_read()
561 xfer[1].addr = i2c->addr; in cdce925_regmap_i2c_read()
566 ret = i2c_transfer(i2c->adapter, xfer, 2); in cdce925_regmap_i2c_read()
568 dev_dbg(&i2c->dev, "%s(%zu, %zu) %#x %#x\n", __func__, in cdce925_regmap_i2c_read()
574 return -EIO; in cdce925_regmap_i2c_read()
581 unsigned int idx = clkspec->args[0]; in of_clk_cdce925_get()
583 if (idx >= ARRAY_SIZE(data->clk)) { in of_clk_cdce925_get()
585 return ERR_PTR(-EINVAL); in of_clk_cdce925_get()
588 return &data->clk[idx].hw; in of_clk_cdce925_get()
602 /* The CDCE925 uses a funky way to read/write registers. Bulk mode is
603 * just weird, so just use the single byte mode exclusively. */
612 struct device_node *node = client->dev.of_node; in cdce925_probe()
628 dev_dbg(&client->dev, "%s\n", __func__); in cdce925_probe()
630 err = cdce925_regulator_enable(&client->dev, "vdd"); in cdce925_probe()
634 err = cdce925_regulator_enable(&client->dev, "vddout"); in cdce925_probe()
638 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); in cdce925_probe()
640 return -ENOMEM; in cdce925_probe()
642 data->i2c_client = client; in cdce925_probe()
643 data->chip_info = i2c_get_match_data(client); in cdce925_probe()
645 data->chip_info->num_plls * 0x10 - 1; in cdce925_probe()
646 data->regmap = devm_regmap_init(&client->dev, ®map_cdce925_bus, in cdce925_probe()
647 &client->dev, &config); in cdce925_probe()
648 if (IS_ERR(data->regmap)) { in cdce925_probe()
649 dev_err(&client->dev, "failed to allocate register map\n"); in cdce925_probe()
650 return PTR_ERR(data->regmap); in cdce925_probe()
656 dev_err(&client->dev, "missing parent clock\n"); in cdce925_probe()
657 return -ENODEV; in cdce925_probe()
659 dev_dbg(&client->dev, "parent is: %s\n", parent_name); in cdce925_probe()
661 if (of_property_read_u32(node, "xtal-load-pf", &value) == 0) in cdce925_probe()
662 regmap_write(data->regmap, in cdce925_probe()
665 regmap_update_bits(data->regmap, CDCE925_REG_GLOBAL1, BIT(4), 0); in cdce925_probe()
668 regmap_update_bits(data->regmap, 0x02, BIT(7), 0); in cdce925_probe()
676 for (i = 0; i < data->chip_info->num_plls; ++i) { in cdce925_probe()
678 client->dev.of_node, i); in cdce925_probe()
680 err = -ENOMEM; in cdce925_probe()
684 data->pll[i].chip = data; in cdce925_probe()
685 data->pll[i].hw.init = &init; in cdce925_probe()
686 data->pll[i].index = i; in cdce925_probe()
687 err = devm_clk_hw_register(&client->dev, &data->pll[i].hw); in cdce925_probe()
689 dev_err(&client->dev, "Failed register PLL %d\n", i); in cdce925_probe()
697 "clock-frequency", &value)) { in cdce925_probe()
698 err = clk_set_rate(data->pll[i].hw.clk, value); in cdce925_probe()
700 dev_err(&client->dev, in cdce925_probe()
705 "spread-spectrum", &value)) { in cdce925_probe()
707 "spread-spectrum-center") ? 0x80 : 0x00; in cdce925_probe()
708 regmap_update_bits(data->regmap, in cdce925_probe()
711 regmap_update_bits(data->regmap, in cdce925_probe()
723 init.name = kasprintf(GFP_KERNEL, "%pOFn.Y1", client->dev.of_node); in cdce925_probe()
725 err = -ENOMEM; in cdce925_probe()
728 data->clk[0].chip = data; in cdce925_probe()
729 data->clk[0].hw.init = &init; in cdce925_probe()
730 data->clk[0].index = 0; in cdce925_probe()
731 data->clk[0].pdiv = 1; in cdce925_probe()
732 err = devm_clk_hw_register(&client->dev, &data->clk[0].hw); in cdce925_probe()
735 dev_err(&client->dev, "clock registration Y1 failed\n"); in cdce925_probe()
743 for (i = 1; i < data->chip_info->num_outputs; ++i) { in cdce925_probe()
745 client->dev.of_node, i+1); in cdce925_probe()
747 err = -ENOMEM; in cdce925_probe()
750 data->clk[i].chip = data; in cdce925_probe()
751 data->clk[i].hw.init = &init; in cdce925_probe()
752 data->clk[i].index = i; in cdce925_probe()
753 data->clk[i].pdiv = 1; in cdce925_probe()
776 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw); in cdce925_probe()
779 dev_err(&client->dev, "clock registration failed\n"); in cdce925_probe()
785 err = of_clk_add_hw_provider(client->dev.of_node, of_clk_cdce925_get, in cdce925_probe()
788 dev_err(&client->dev, "unable to add OF clock provider\n"); in cdce925_probe()
793 for (i = 0; i < data->chip_info->num_plls; ++i) in cdce925_probe()