1f3867f43SBen Skeggs /*
2af6313d6SAlexandre Courbot * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3f3867f43SBen Skeggs *
4f3867f43SBen Skeggs * Permission is hereby granted, free of charge, to any person obtaining a
5f3867f43SBen Skeggs * copy of this software and associated documentation files (the "Software"),
6f3867f43SBen Skeggs * to deal in the Software without restriction, including without limitation
7f3867f43SBen Skeggs * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8f3867f43SBen Skeggs * and/or sell copies of the Software, and to permit persons to whom the
9f3867f43SBen Skeggs * Software is furnished to do so, subject to the following conditions:
10f3867f43SBen Skeggs *
11f3867f43SBen Skeggs * The above copyright notice and this permission notice shall be included in
12f3867f43SBen Skeggs * all copies or substantial portions of the Software.
13f3867f43SBen Skeggs *
14f3867f43SBen Skeggs * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15f3867f43SBen Skeggs * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16f3867f43SBen Skeggs * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17f3867f43SBen Skeggs * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18f3867f43SBen Skeggs * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19f3867f43SBen Skeggs * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20f3867f43SBen Skeggs * DEALINGS IN THE SOFTWARE.
21f3867f43SBen Skeggs *
22f3867f43SBen Skeggs * Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c
23f3867f43SBen Skeggs *
24f3867f43SBen Skeggs */
256625f55cSBen Skeggs #include "priv.h"
2642d6e167SAlexandre Courbot #include "gk20a.h"
276625f55cSBen Skeggs
2843a70661SBen Skeggs #include <core/tegra.h>
297632b30eSBen Skeggs #include <subdev/timer.h>
307632b30eSBen Skeggs
31195c1137SAlexandre Courbot static const u8 _pl_to_div[] = {
32f3867f43SBen Skeggs /* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
33f3867f43SBen Skeggs /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32,
34f3867f43SBen Skeggs };
35f3867f43SBen Skeggs
pl_to_div(u32 pl)36195c1137SAlexandre Courbot static u32 pl_to_div(u32 pl)
37195c1137SAlexandre Courbot {
38195c1137SAlexandre Courbot if (pl >= ARRAY_SIZE(_pl_to_div))
39195c1137SAlexandre Courbot return 1;
40195c1137SAlexandre Courbot
41195c1137SAlexandre Courbot return _pl_to_div[pl];
42195c1137SAlexandre Courbot }
43195c1137SAlexandre Courbot
div_to_pl(u32 div)44195c1137SAlexandre Courbot static u32 div_to_pl(u32 div)
45195c1137SAlexandre Courbot {
46195c1137SAlexandre Courbot u32 pl;
47195c1137SAlexandre Courbot
48195c1137SAlexandre Courbot for (pl = 0; pl < ARRAY_SIZE(_pl_to_div) - 1; pl++) {
49195c1137SAlexandre Courbot if (_pl_to_div[pl] >= div)
50195c1137SAlexandre Courbot return pl;
51195c1137SAlexandre Courbot }
52195c1137SAlexandre Courbot
53195c1137SAlexandre Courbot return ARRAY_SIZE(_pl_to_div) - 1;
54195c1137SAlexandre Courbot }
55f3867f43SBen Skeggs
56f3867f43SBen Skeggs static const struct gk20a_clk_pllg_params gk20a_pllg_params = {
57af6313d6SAlexandre Courbot .min_vco = 1000000, .max_vco = 2064000,
58af6313d6SAlexandre Courbot .min_u = 12000, .max_u = 38000,
59f3867f43SBen Skeggs .min_m = 1, .max_m = 255,
60f3867f43SBen Skeggs .min_n = 8, .max_n = 255,
61f3867f43SBen Skeggs .min_pl = 1, .max_pl = 32,
62f3867f43SBen Skeggs };
63f3867f43SBen Skeggs
6422b6c9e8SAlexandre Courbot void
gk20a_pllg_read_mnp(struct gk20a_clk * clk,struct gk20a_pll * pll)65a04bc140SAlexandre Courbot gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll)
66f3867f43SBen Skeggs {
67822ad79fSBen Skeggs struct nvkm_device *device = clk->base.subdev.device;
68f3867f43SBen Skeggs u32 val;
69f3867f43SBen Skeggs
70822ad79fSBen Skeggs val = nvkm_rd32(device, GPCPLL_COEFF);
71a04bc140SAlexandre Courbot pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
72a04bc140SAlexandre Courbot pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH);
73a04bc140SAlexandre Courbot pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);
74f3867f43SBen Skeggs }
75f3867f43SBen Skeggs
7622b6c9e8SAlexandre Courbot void
gk20a_pllg_write_mnp(struct gk20a_clk * clk,const struct gk20a_pll * pll)77a9608c9bSAlexandre Courbot gk20a_pllg_write_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll)
78a9608c9bSAlexandre Courbot {
79a9608c9bSAlexandre Courbot struct nvkm_device *device = clk->base.subdev.device;
80a9608c9bSAlexandre Courbot u32 val;
81a9608c9bSAlexandre Courbot
82a9608c9bSAlexandre Courbot val = (pll->m & MASK(GPCPLL_COEFF_M_WIDTH)) << GPCPLL_COEFF_M_SHIFT;
83a9608c9bSAlexandre Courbot val |= (pll->n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT;
84a9608c9bSAlexandre Courbot val |= (pll->pl & MASK(GPCPLL_COEFF_P_WIDTH)) << GPCPLL_COEFF_P_SHIFT;
85a9608c9bSAlexandre Courbot nvkm_wr32(device, GPCPLL_COEFF, val);
86a9608c9bSAlexandre Courbot }
87a9608c9bSAlexandre Courbot
8822b6c9e8SAlexandre Courbot u32
gk20a_pllg_calc_rate(struct gk20a_clk * clk,struct gk20a_pll * pll)8989d3a912SAlexandre Courbot gk20a_pllg_calc_rate(struct gk20a_clk *clk, struct gk20a_pll *pll)
90f3867f43SBen Skeggs {
91f3867f43SBen Skeggs u32 rate;
92f3867f43SBen Skeggs u32 divider;
93f3867f43SBen Skeggs
9489d3a912SAlexandre Courbot rate = clk->parent_rate * pll->n;
9589d3a912SAlexandre Courbot divider = pll->m * clk->pl_to_div(pll->pl);
96f3867f43SBen Skeggs
978cb87c04SNicolas Pitre return rate / divider / 2;
98f3867f43SBen Skeggs }
99f3867f43SBen Skeggs
10022b6c9e8SAlexandre Courbot int
gk20a_pllg_calc_mnp(struct gk20a_clk * clk,unsigned long rate,struct gk20a_pll * pll)10189d3a912SAlexandre Courbot gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate,
10289d3a912SAlexandre Courbot struct gk20a_pll *pll)
103f3867f43SBen Skeggs {
104b907649eSBen Skeggs struct nvkm_subdev *subdev = &clk->base.subdev;
105f3867f43SBen Skeggs u32 target_clk_f, ref_clk_f, target_freq;
106f3867f43SBen Skeggs u32 min_vco_f, max_vco_f;
107f3867f43SBen Skeggs u32 low_pl, high_pl, best_pl;
108d865f3c5SAlexandre Courbot u32 target_vco_f;
109f3867f43SBen Skeggs u32 best_m, best_n;
110d865f3c5SAlexandre Courbot u32 best_delta = ~0;
111f3867f43SBen Skeggs u32 pl;
112f3867f43SBen Skeggs
113af6313d6SAlexandre Courbot target_clk_f = rate * 2 / KHZ;
114af6313d6SAlexandre Courbot ref_clk_f = clk->parent_rate / KHZ;
115f3867f43SBen Skeggs
116d7ca1106SAlexandre Courbot target_vco_f = target_clk_f + target_clk_f / 50;
117d7ca1106SAlexandre Courbot max_vco_f = max(clk->params->max_vco, target_vco_f);
1183eca809bSBen Skeggs min_vco_f = clk->params->min_vco;
1193eca809bSBen Skeggs best_m = clk->params->max_m;
1203eca809bSBen Skeggs best_n = clk->params->min_n;
1213eca809bSBen Skeggs best_pl = clk->params->min_pl;
122f3867f43SBen Skeggs
123f3867f43SBen Skeggs /* min_pl <= high_pl <= max_pl */
124f3867f43SBen Skeggs high_pl = (max_vco_f + target_vco_f - 1) / target_vco_f;
1253eca809bSBen Skeggs high_pl = min(high_pl, clk->params->max_pl);
1263eca809bSBen Skeggs high_pl = max(high_pl, clk->params->min_pl);
127195c1137SAlexandre Courbot high_pl = clk->div_to_pl(high_pl);
128f3867f43SBen Skeggs
129f3867f43SBen Skeggs /* min_pl <= low_pl <= max_pl */
130f3867f43SBen Skeggs low_pl = min_vco_f / target_vco_f;
1313eca809bSBen Skeggs low_pl = min(low_pl, clk->params->max_pl);
1323eca809bSBen Skeggs low_pl = max(low_pl, clk->params->min_pl);
133195c1137SAlexandre Courbot low_pl = clk->div_to_pl(low_pl);
134f3867f43SBen Skeggs
135b907649eSBen Skeggs nvkm_debug(subdev, "low_PL %d(div%d), high_PL %d(div%d)", low_pl,
136195c1137SAlexandre Courbot clk->pl_to_div(low_pl), high_pl, clk->pl_to_div(high_pl));
137f3867f43SBen Skeggs
138f3867f43SBen Skeggs /* Select lowest possible VCO */
139f3867f43SBen Skeggs for (pl = low_pl; pl <= high_pl; pl++) {
140d865f3c5SAlexandre Courbot u32 m, n, n2;
141d865f3c5SAlexandre Courbot
142195c1137SAlexandre Courbot target_vco_f = target_clk_f * clk->pl_to_div(pl);
143195c1137SAlexandre Courbot
1443eca809bSBen Skeggs for (m = clk->params->min_m; m <= clk->params->max_m; m++) {
145d7ca1106SAlexandre Courbot u32 u_f = ref_clk_f / m;
146f3867f43SBen Skeggs
1473eca809bSBen Skeggs if (u_f < clk->params->min_u)
148f3867f43SBen Skeggs break;
1493eca809bSBen Skeggs if (u_f > clk->params->max_u)
150f3867f43SBen Skeggs continue;
151f3867f43SBen Skeggs
152f3867f43SBen Skeggs n = (target_vco_f * m) / ref_clk_f;
153f3867f43SBen Skeggs n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f;
154f3867f43SBen Skeggs
1553eca809bSBen Skeggs if (n > clk->params->max_n)
156f3867f43SBen Skeggs break;
157f3867f43SBen Skeggs
158f3867f43SBen Skeggs for (; n <= n2; n++) {
159d7ca1106SAlexandre Courbot u32 vco_f;
160d7ca1106SAlexandre Courbot
1613eca809bSBen Skeggs if (n < clk->params->min_n)
162f3867f43SBen Skeggs continue;
1633eca809bSBen Skeggs if (n > clk->params->max_n)
164f3867f43SBen Skeggs break;
165f3867f43SBen Skeggs
166f3867f43SBen Skeggs vco_f = ref_clk_f * n / m;
167f3867f43SBen Skeggs
168f3867f43SBen Skeggs if (vco_f >= min_vco_f && vco_f <= max_vco_f) {
169d865f3c5SAlexandre Courbot u32 delta, lwv;
170d865f3c5SAlexandre Courbot
171195c1137SAlexandre Courbot lwv = (vco_f + (clk->pl_to_div(pl) / 2))
172195c1137SAlexandre Courbot / clk->pl_to_div(pl);
173f3867f43SBen Skeggs delta = abs(lwv - target_clk_f);
174f3867f43SBen Skeggs
175f3867f43SBen Skeggs if (delta < best_delta) {
176f3867f43SBen Skeggs best_delta = delta;
177f3867f43SBen Skeggs best_m = m;
178f3867f43SBen Skeggs best_n = n;
179f3867f43SBen Skeggs best_pl = pl;
180f3867f43SBen Skeggs
181f3867f43SBen Skeggs if (best_delta == 0)
182f3867f43SBen Skeggs goto found_match;
183f3867f43SBen Skeggs }
184f3867f43SBen Skeggs }
185f3867f43SBen Skeggs }
186f3867f43SBen Skeggs }
187f3867f43SBen Skeggs }
188f3867f43SBen Skeggs
189f3867f43SBen Skeggs found_match:
190f3867f43SBen Skeggs WARN_ON(best_delta == ~0);
191f3867f43SBen Skeggs
192f3867f43SBen Skeggs if (best_delta != 0)
193b907649eSBen Skeggs nvkm_debug(subdev,
194b907649eSBen Skeggs "no best match for target @ %dMHz on gpc_pll",
195af6313d6SAlexandre Courbot target_clk_f / KHZ);
196f3867f43SBen Skeggs
19789d3a912SAlexandre Courbot pll->m = best_m;
19889d3a912SAlexandre Courbot pll->n = best_n;
19989d3a912SAlexandre Courbot pll->pl = best_pl;
200f3867f43SBen Skeggs
20189d3a912SAlexandre Courbot target_freq = gk20a_pllg_calc_rate(clk, pll);
202f3867f43SBen Skeggs
203b907649eSBen Skeggs nvkm_debug(subdev,
20489d3a912SAlexandre Courbot "actual target freq %d KHz, M %d, N %d, PL %d(div%d)\n",
20589d3a912SAlexandre Courbot target_freq / KHZ, pll->m, pll->n, pll->pl,
20689d3a912SAlexandre Courbot clk->pl_to_div(pll->pl));
207f3867f43SBen Skeggs return 0;
208f3867f43SBen Skeggs }
209f3867f43SBen Skeggs
210f3867f43SBen Skeggs static int
gk20a_pllg_slide(struct gk20a_clk * clk,u32 n)2113eca809bSBen Skeggs gk20a_pllg_slide(struct gk20a_clk *clk, u32 n)
212f3867f43SBen Skeggs {
213b907649eSBen Skeggs struct nvkm_subdev *subdev = &clk->base.subdev;
214b907649eSBen Skeggs struct nvkm_device *device = subdev->device;
215a9608c9bSAlexandre Courbot struct gk20a_pll pll;
2169102240cSAlexandre Courbot int ret = 0;
217f3867f43SBen Skeggs
218f3867f43SBen Skeggs /* get old coefficients */
219a9608c9bSAlexandre Courbot gk20a_pllg_read_mnp(clk, &pll);
220f3867f43SBen Skeggs /* do nothing if NDIV is the same */
221a9608c9bSAlexandre Courbot if (n == pll.n)
222f3867f43SBen Skeggs return 0;
223f3867f43SBen Skeggs
224f3867f43SBen Skeggs /* pll slowdown mode */
225822ad79fSBen Skeggs nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN,
226f3867f43SBen Skeggs BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT),
227f3867f43SBen Skeggs BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT));
228f3867f43SBen Skeggs
229f3867f43SBen Skeggs /* new ndiv ready for ramp */
230a9608c9bSAlexandre Courbot pll.n = n;
231f3867f43SBen Skeggs udelay(1);
232a9608c9bSAlexandre Courbot gk20a_pllg_write_mnp(clk, &pll);
233f3867f43SBen Skeggs
234f3867f43SBen Skeggs /* dynamic ramp to new ndiv */
235f3867f43SBen Skeggs udelay(1);
2369102240cSAlexandre Courbot nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN,
2379102240cSAlexandre Courbot BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT),
2389102240cSAlexandre Courbot BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT));
239f3867f43SBen Skeggs
2409102240cSAlexandre Courbot /* wait for ramping to complete */
2419102240cSAlexandre Courbot if (nvkm_wait_usec(device, 500, GPC_BCAST_NDIV_SLOWDOWN_DEBUG,
2429102240cSAlexandre Courbot GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK,
2439102240cSAlexandre Courbot GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK) < 0)
2449102240cSAlexandre Courbot ret = -ETIMEDOUT;
245f3867f43SBen Skeggs
246f3867f43SBen Skeggs /* exit slowdown mode */
247822ad79fSBen Skeggs nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN,
248f3867f43SBen Skeggs BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT) |
249f3867f43SBen Skeggs BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), 0);
250822ad79fSBen Skeggs nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN);
251f3867f43SBen Skeggs
2529102240cSAlexandre Courbot return ret;
253f3867f43SBen Skeggs }
254f3867f43SBen Skeggs
2556ed7e742SAlexandre Courbot static int
gk20a_pllg_enable(struct gk20a_clk * clk)256e7952eb6SAlexandre Courbot gk20a_pllg_enable(struct gk20a_clk *clk)
257f3867f43SBen Skeggs {
258822ad79fSBen Skeggs struct nvkm_device *device = clk->base.subdev.device;
2596ed7e742SAlexandre Courbot u32 val;
260e7952eb6SAlexandre Courbot
261822ad79fSBen Skeggs nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE);
262822ad79fSBen Skeggs nvkm_rd32(device, GPCPLL_CFG);
2636ed7e742SAlexandre Courbot
2646ed7e742SAlexandre Courbot /* enable lock detection */
2656ed7e742SAlexandre Courbot val = nvkm_rd32(device, GPCPLL_CFG);
2666ed7e742SAlexandre Courbot if (val & GPCPLL_CFG_LOCK_DET_OFF) {
2676ed7e742SAlexandre Courbot val &= ~GPCPLL_CFG_LOCK_DET_OFF;
2686ed7e742SAlexandre Courbot nvkm_wr32(device, GPCPLL_CFG, val);
2696ed7e742SAlexandre Courbot }
2706ed7e742SAlexandre Courbot
2716ed7e742SAlexandre Courbot /* wait for lock */
2726ed7e742SAlexandre Courbot if (nvkm_wait_usec(device, 300, GPCPLL_CFG, GPCPLL_CFG_LOCK,
2736ed7e742SAlexandre Courbot GPCPLL_CFG_LOCK) < 0)
2746ed7e742SAlexandre Courbot return -ETIMEDOUT;
2756ed7e742SAlexandre Courbot
2766ed7e742SAlexandre Courbot /* switch to VCO mode */
2776ed7e742SAlexandre Courbot nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT),
2786ed7e742SAlexandre Courbot BIT(SEL_VCO_GPC2CLK_OUT_SHIFT));
2796ed7e742SAlexandre Courbot
2806ed7e742SAlexandre Courbot return 0;
281f3867f43SBen Skeggs }
282f3867f43SBen Skeggs
283f3867f43SBen Skeggs static void
gk20a_pllg_disable(struct gk20a_clk * clk)284e7952eb6SAlexandre Courbot gk20a_pllg_disable(struct gk20a_clk *clk)
285f3867f43SBen Skeggs {
286822ad79fSBen Skeggs struct nvkm_device *device = clk->base.subdev.device;
287e7952eb6SAlexandre Courbot
2886ed7e742SAlexandre Courbot /* put PLL in bypass before disabling it */
2896ed7e742SAlexandre Courbot nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0);
2906ed7e742SAlexandre Courbot
291822ad79fSBen Skeggs nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0);
292822ad79fSBen Skeggs nvkm_rd32(device, GPCPLL_CFG);
293f3867f43SBen Skeggs }
294f3867f43SBen Skeggs
295f3867f43SBen Skeggs static int
gk20a_pllg_program_mnp(struct gk20a_clk * clk,const struct gk20a_pll * pll)2966ed7e742SAlexandre Courbot gk20a_pllg_program_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll)
297f3867f43SBen Skeggs {
298b907649eSBen Skeggs struct nvkm_subdev *subdev = &clk->base.subdev;
299b907649eSBen Skeggs struct nvkm_device *device = subdev->device;
3006ed7e742SAlexandre Courbot struct gk20a_pll cur_pll;
301a08c8baeSAlexandre Courbot int ret;
302a08c8baeSAlexandre Courbot
3036ed7e742SAlexandre Courbot gk20a_pllg_read_mnp(clk, &cur_pll);
3046ed7e742SAlexandre Courbot
3056ed7e742SAlexandre Courbot /* split VCO-to-bypass jump in half by setting out divider 1:2 */
3066ed7e742SAlexandre Courbot nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,
3076ed7e742SAlexandre Courbot GPC2CLK_OUT_VCODIV2 << GPC2CLK_OUT_VCODIV_SHIFT);
3086ed7e742SAlexandre Courbot /* Intentional 2nd write to assure linear divider operation */
3096ed7e742SAlexandre Courbot nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,
3106ed7e742SAlexandre Courbot GPC2CLK_OUT_VCODIV2 << GPC2CLK_OUT_VCODIV_SHIFT);
3116ed7e742SAlexandre Courbot nvkm_rd32(device, GPC2CLK_OUT);
3126ed7e742SAlexandre Courbot udelay(2);
3136ed7e742SAlexandre Courbot
3146ed7e742SAlexandre Courbot gk20a_pllg_disable(clk);
3156ed7e742SAlexandre Courbot
3166ed7e742SAlexandre Courbot gk20a_pllg_write_mnp(clk, pll);
3176ed7e742SAlexandre Courbot
3186ed7e742SAlexandre Courbot ret = gk20a_pllg_enable(clk);
3196ed7e742SAlexandre Courbot if (ret)
3206ed7e742SAlexandre Courbot return ret;
3216ed7e742SAlexandre Courbot
3226ed7e742SAlexandre Courbot /* restore out divider 1:1 */
3236ed7e742SAlexandre Courbot udelay(2);
3246ed7e742SAlexandre Courbot nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,
3256ed7e742SAlexandre Courbot GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT);
3266ed7e742SAlexandre Courbot /* Intentional 2nd write to assure linear divider operation */
3276ed7e742SAlexandre Courbot nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,
3286ed7e742SAlexandre Courbot GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT);
3296ed7e742SAlexandre Courbot nvkm_rd32(device, GPC2CLK_OUT);
3306ed7e742SAlexandre Courbot
3316ed7e742SAlexandre Courbot return 0;
3326ed7e742SAlexandre Courbot }
3336ed7e742SAlexandre Courbot
3346ed7e742SAlexandre Courbot static int
gk20a_pllg_program_mnp_slide(struct gk20a_clk * clk,const struct gk20a_pll * pll)3356ed7e742SAlexandre Courbot gk20a_pllg_program_mnp_slide(struct gk20a_clk *clk, const struct gk20a_pll *pll)
3366ed7e742SAlexandre Courbot {
3376ed7e742SAlexandre Courbot struct gk20a_pll cur_pll;
3386ed7e742SAlexandre Courbot int ret;
3396ed7e742SAlexandre Courbot
3406ed7e742SAlexandre Courbot if (gk20a_pllg_is_enabled(clk)) {
3416ed7e742SAlexandre Courbot gk20a_pllg_read_mnp(clk, &cur_pll);
3426ed7e742SAlexandre Courbot
3436ed7e742SAlexandre Courbot /* just do NDIV slide if there is no change to M and PL */
3446ed7e742SAlexandre Courbot if (pll->m == cur_pll.m && pll->pl == cur_pll.pl)
3456ed7e742SAlexandre Courbot return gk20a_pllg_slide(clk, pll->n);
3466ed7e742SAlexandre Courbot
3476ed7e742SAlexandre Courbot /* slide down to current NDIV_LO */
3486ed7e742SAlexandre Courbot cur_pll.n = gk20a_pllg_n_lo(clk, &cur_pll);
3496ed7e742SAlexandre Courbot ret = gk20a_pllg_slide(clk, cur_pll.n);
350f3867f43SBen Skeggs if (ret)
351f3867f43SBen Skeggs return ret;
352f3867f43SBen Skeggs }
353f3867f43SBen Skeggs
3546ed7e742SAlexandre Courbot /* program MNP with the new clock parameters and new NDIV_LO */
3556ed7e742SAlexandre Courbot cur_pll = *pll;
3566ed7e742SAlexandre Courbot cur_pll.n = gk20a_pllg_n_lo(clk, &cur_pll);
3576ed7e742SAlexandre Courbot ret = gk20a_pllg_program_mnp(clk, &cur_pll);
3586ed7e742SAlexandre Courbot if (ret)
3596ed7e742SAlexandre Courbot return ret;
360f3867f43SBen Skeggs
361f3867f43SBen Skeggs /* slide up to new NDIV */
3626ed7e742SAlexandre Courbot return gk20a_pllg_slide(clk, pll->n);
363f3867f43SBen Skeggs }
364f3867f43SBen Skeggs
3657632b30eSBen Skeggs static struct nvkm_pstate
366f3867f43SBen Skeggs gk20a_pstates[] = {
367f3867f43SBen Skeggs {
368f3867f43SBen Skeggs .base = {
369f3867f43SBen Skeggs .domain[nv_clk_src_gpc] = 72000,
370f3867f43SBen Skeggs .voltage = 0,
371f3867f43SBen Skeggs },
372f3867f43SBen Skeggs },
373f3867f43SBen Skeggs {
374f3867f43SBen Skeggs .base = {
375f3867f43SBen Skeggs .domain[nv_clk_src_gpc] = 108000,
376f3867f43SBen Skeggs .voltage = 1,
377f3867f43SBen Skeggs },
378f3867f43SBen Skeggs },
379f3867f43SBen Skeggs {
380f3867f43SBen Skeggs .base = {
381f3867f43SBen Skeggs .domain[nv_clk_src_gpc] = 180000,
382f3867f43SBen Skeggs .voltage = 2,
383f3867f43SBen Skeggs },
384f3867f43SBen Skeggs },
385f3867f43SBen Skeggs {
386f3867f43SBen Skeggs .base = {
387f3867f43SBen Skeggs .domain[nv_clk_src_gpc] = 252000,
388f3867f43SBen Skeggs .voltage = 3,
389f3867f43SBen Skeggs },
390f3867f43SBen Skeggs },
391f3867f43SBen Skeggs {
392f3867f43SBen Skeggs .base = {
393f3867f43SBen Skeggs .domain[nv_clk_src_gpc] = 324000,
394f3867f43SBen Skeggs .voltage = 4,
395f3867f43SBen Skeggs },
396f3867f43SBen Skeggs },
397f3867f43SBen Skeggs {
398f3867f43SBen Skeggs .base = {
399f3867f43SBen Skeggs .domain[nv_clk_src_gpc] = 396000,
400f3867f43SBen Skeggs .voltage = 5,
401f3867f43SBen Skeggs },
402f3867f43SBen Skeggs },
403f3867f43SBen Skeggs {
404f3867f43SBen Skeggs .base = {
405f3867f43SBen Skeggs .domain[nv_clk_src_gpc] = 468000,
406f3867f43SBen Skeggs .voltage = 6,
407f3867f43SBen Skeggs },
408f3867f43SBen Skeggs },
409f3867f43SBen Skeggs {
410f3867f43SBen Skeggs .base = {
411f3867f43SBen Skeggs .domain[nv_clk_src_gpc] = 540000,
412f3867f43SBen Skeggs .voltage = 7,
413f3867f43SBen Skeggs },
414f3867f43SBen Skeggs },
415f3867f43SBen Skeggs {
416f3867f43SBen Skeggs .base = {
417f3867f43SBen Skeggs .domain[nv_clk_src_gpc] = 612000,
418f3867f43SBen Skeggs .voltage = 8,
419f3867f43SBen Skeggs },
420f3867f43SBen Skeggs },
421f3867f43SBen Skeggs {
422f3867f43SBen Skeggs .base = {
423f3867f43SBen Skeggs .domain[nv_clk_src_gpc] = 648000,
424f3867f43SBen Skeggs .voltage = 9,
425f3867f43SBen Skeggs },
426f3867f43SBen Skeggs },
427f3867f43SBen Skeggs {
428f3867f43SBen Skeggs .base = {
429f3867f43SBen Skeggs .domain[nv_clk_src_gpc] = 684000,
430f3867f43SBen Skeggs .voltage = 10,
431f3867f43SBen Skeggs },
432f3867f43SBen Skeggs },
433f3867f43SBen Skeggs {
434f3867f43SBen Skeggs .base = {
435f3867f43SBen Skeggs .domain[nv_clk_src_gpc] = 708000,
436f3867f43SBen Skeggs .voltage = 11,
437f3867f43SBen Skeggs },
438f3867f43SBen Skeggs },
439f3867f43SBen Skeggs {
440f3867f43SBen Skeggs .base = {
441f3867f43SBen Skeggs .domain[nv_clk_src_gpc] = 756000,
442f3867f43SBen Skeggs .voltage = 12,
443f3867f43SBen Skeggs },
444f3867f43SBen Skeggs },
445f3867f43SBen Skeggs {
446f3867f43SBen Skeggs .base = {
447f3867f43SBen Skeggs .domain[nv_clk_src_gpc] = 804000,
448f3867f43SBen Skeggs .voltage = 13,
449f3867f43SBen Skeggs },
450f3867f43SBen Skeggs },
451f3867f43SBen Skeggs {
452f3867f43SBen Skeggs .base = {
453f3867f43SBen Skeggs .domain[nv_clk_src_gpc] = 852000,
454f3867f43SBen Skeggs .voltage = 14,
455f3867f43SBen Skeggs },
456f3867f43SBen Skeggs },
457f3867f43SBen Skeggs };
458f3867f43SBen Skeggs
45942d6e167SAlexandre Courbot int
gk20a_clk_read(struct nvkm_clk * base,enum nv_clk_src src)4606625f55cSBen Skeggs gk20a_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
461f3867f43SBen Skeggs {
4626625f55cSBen Skeggs struct gk20a_clk *clk = gk20a_clk(base);
463b907649eSBen Skeggs struct nvkm_subdev *subdev = &clk->base.subdev;
464b907649eSBen Skeggs struct nvkm_device *device = subdev->device;
46589d3a912SAlexandre Courbot struct gk20a_pll pll;
466f3867f43SBen Skeggs
467f3867f43SBen Skeggs switch (src) {
468f3867f43SBen Skeggs case nv_clk_src_crystal:
469822ad79fSBen Skeggs return device->crystal;
470f3867f43SBen Skeggs case nv_clk_src_gpc:
47189d3a912SAlexandre Courbot gk20a_pllg_read_mnp(clk, &pll);
47289d3a912SAlexandre Courbot return gk20a_pllg_calc_rate(clk, &pll) / GK20A_CLK_GPC_MDIV;
473f3867f43SBen Skeggs default:
474b907649eSBen Skeggs nvkm_error(subdev, "invalid clock source %d\n", src);
475f3867f43SBen Skeggs return -EINVAL;
476f3867f43SBen Skeggs }
477f3867f43SBen Skeggs }
478f3867f43SBen Skeggs
47942d6e167SAlexandre Courbot int
gk20a_clk_calc(struct nvkm_clk * base,struct nvkm_cstate * cstate)4806625f55cSBen Skeggs gk20a_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
481f3867f43SBen Skeggs {
4826625f55cSBen Skeggs struct gk20a_clk *clk = gk20a_clk(base);
483f3867f43SBen Skeggs
4843eca809bSBen Skeggs return gk20a_pllg_calc_mnp(clk, cstate->domain[nv_clk_src_gpc] *
48589d3a912SAlexandre Courbot GK20A_CLK_GPC_MDIV, &clk->pll);
486f3867f43SBen Skeggs }
487f3867f43SBen Skeggs
48842d6e167SAlexandre Courbot int
gk20a_clk_prog(struct nvkm_clk * base)4896625f55cSBen Skeggs gk20a_clk_prog(struct nvkm_clk *base)
490f3867f43SBen Skeggs {
4916625f55cSBen Skeggs struct gk20a_clk *clk = gk20a_clk(base);
4926ed7e742SAlexandre Courbot int ret;
493f3867f43SBen Skeggs
4946ed7e742SAlexandre Courbot ret = gk20a_pllg_program_mnp_slide(clk, &clk->pll);
4956ed7e742SAlexandre Courbot if (ret)
4966ed7e742SAlexandre Courbot ret = gk20a_pllg_program_mnp(clk, &clk->pll);
4976ed7e742SAlexandre Courbot
4986ed7e742SAlexandre Courbot return ret;
499f3867f43SBen Skeggs }
500f3867f43SBen Skeggs
50142d6e167SAlexandre Courbot void
gk20a_clk_tidy(struct nvkm_clk * base)5026625f55cSBen Skeggs gk20a_clk_tidy(struct nvkm_clk *base)
503f3867f43SBen Skeggs {
504f3867f43SBen Skeggs }
505f3867f43SBen Skeggs
506f5f1b06eSAlexandre Courbot int
gk20a_clk_setup_slide(struct gk20a_clk * clk)507f5f1b06eSAlexandre Courbot gk20a_clk_setup_slide(struct gk20a_clk *clk)
508f5f1b06eSAlexandre Courbot {
509f5f1b06eSAlexandre Courbot struct nvkm_subdev *subdev = &clk->base.subdev;
510f5f1b06eSAlexandre Courbot struct nvkm_device *device = subdev->device;
511f5f1b06eSAlexandre Courbot u32 step_a, step_b;
512f5f1b06eSAlexandre Courbot
513f5f1b06eSAlexandre Courbot switch (clk->parent_rate) {
514f5f1b06eSAlexandre Courbot case 12000000:
515f5f1b06eSAlexandre Courbot case 12800000:
516f5f1b06eSAlexandre Courbot case 13000000:
517f5f1b06eSAlexandre Courbot step_a = 0x2b;
518f5f1b06eSAlexandre Courbot step_b = 0x0b;
519f5f1b06eSAlexandre Courbot break;
520f5f1b06eSAlexandre Courbot case 19200000:
521f5f1b06eSAlexandre Courbot step_a = 0x12;
522f5f1b06eSAlexandre Courbot step_b = 0x08;
523f5f1b06eSAlexandre Courbot break;
524f5f1b06eSAlexandre Courbot case 38400000:
525f5f1b06eSAlexandre Courbot step_a = 0x04;
526f5f1b06eSAlexandre Courbot step_b = 0x05;
527f5f1b06eSAlexandre Courbot break;
528f5f1b06eSAlexandre Courbot default:
529f5f1b06eSAlexandre Courbot nvkm_error(subdev, "invalid parent clock rate %u KHz",
530f5f1b06eSAlexandre Courbot clk->parent_rate / KHZ);
531f5f1b06eSAlexandre Courbot return -EINVAL;
532f5f1b06eSAlexandre Courbot }
533f5f1b06eSAlexandre Courbot
534f5f1b06eSAlexandre Courbot nvkm_mask(device, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT,
535f5f1b06eSAlexandre Courbot step_a << GPCPLL_CFG2_PLL_STEPA_SHIFT);
536f5f1b06eSAlexandre Courbot nvkm_mask(device, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT,
537f5f1b06eSAlexandre Courbot step_b << GPCPLL_CFG3_PLL_STEPB_SHIFT);
538f5f1b06eSAlexandre Courbot
539f5f1b06eSAlexandre Courbot return 0;
540f5f1b06eSAlexandre Courbot }
541f5f1b06eSAlexandre Courbot
54242d6e167SAlexandre Courbot void
gk20a_clk_fini(struct nvkm_clk * base)5436625f55cSBen Skeggs gk20a_clk_fini(struct nvkm_clk *base)
544f3867f43SBen Skeggs {
545e7952eb6SAlexandre Courbot struct nvkm_device *device = base->subdev.device;
5466625f55cSBen Skeggs struct gk20a_clk *clk = gk20a_clk(base);
547e7952eb6SAlexandre Courbot
548e7952eb6SAlexandre Courbot /* slide to VCO min */
5496ed7e742SAlexandre Courbot if (gk20a_pllg_is_enabled(clk)) {
550a04bc140SAlexandre Courbot struct gk20a_pll pll;
551a04bc140SAlexandre Courbot u32 n_lo;
552e7952eb6SAlexandre Courbot
553a04bc140SAlexandre Courbot gk20a_pllg_read_mnp(clk, &pll);
554afea21c9SAlexandre Courbot n_lo = gk20a_pllg_n_lo(clk, &pll);
555e7952eb6SAlexandre Courbot gk20a_pllg_slide(clk, n_lo);
556e7952eb6SAlexandre Courbot }
557e7952eb6SAlexandre Courbot
5583eca809bSBen Skeggs gk20a_pllg_disable(clk);
5596ed7e742SAlexandre Courbot
5606ed7e742SAlexandre Courbot /* set IDDQ */
5616ed7e742SAlexandre Courbot nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_IDDQ, 1);
562f3867f43SBen Skeggs }
563f3867f43SBen Skeggs
564f3867f43SBen Skeggs static int
gk20a_clk_init(struct nvkm_clk * base)5656625f55cSBen Skeggs gk20a_clk_init(struct nvkm_clk *base)
566f3867f43SBen Skeggs {
5676625f55cSBen Skeggs struct gk20a_clk *clk = gk20a_clk(base);
568b907649eSBen Skeggs struct nvkm_subdev *subdev = &clk->base.subdev;
569b907649eSBen Skeggs struct nvkm_device *device = subdev->device;
570f3867f43SBen Skeggs int ret;
571f3867f43SBen Skeggs
5726ed7e742SAlexandre Courbot /* get out from IDDQ */
5736ed7e742SAlexandre Courbot nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_IDDQ, 0);
5746ed7e742SAlexandre Courbot nvkm_rd32(device, GPCPLL_CFG);
5756ed7e742SAlexandre Courbot udelay(5);
5766ed7e742SAlexandre Courbot
5776871b34aSAlexandre Courbot nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK,
5786871b34aSAlexandre Courbot GPC2CLK_OUT_INIT_VAL);
579f3867f43SBen Skeggs
580f5f1b06eSAlexandre Courbot ret = gk20a_clk_setup_slide(clk);
581f5f1b06eSAlexandre Courbot if (ret)
582f5f1b06eSAlexandre Courbot return ret;
583f5f1b06eSAlexandre Courbot
5846871b34aSAlexandre Courbot /* Start with lowest frequency */
5856871b34aSAlexandre Courbot base->func->calc(base, &base->func->pstates[0].base);
5866871b34aSAlexandre Courbot ret = base->func->prog(&clk->base);
587f3867f43SBen Skeggs if (ret) {
588b907649eSBen Skeggs nvkm_error(subdev, "cannot initialize clock\n");
589f3867f43SBen Skeggs return ret;
590f3867f43SBen Skeggs }
591f3867f43SBen Skeggs
592f3867f43SBen Skeggs return 0;
593f3867f43SBen Skeggs }
594f3867f43SBen Skeggs
5956625f55cSBen Skeggs static const struct nvkm_clk_func
5966625f55cSBen Skeggs gk20a_clk = {
5976625f55cSBen Skeggs .init = gk20a_clk_init,
5986625f55cSBen Skeggs .fini = gk20a_clk_fini,
5996625f55cSBen Skeggs .read = gk20a_clk_read,
6006625f55cSBen Skeggs .calc = gk20a_clk_calc,
6016625f55cSBen Skeggs .prog = gk20a_clk_prog,
6026625f55cSBen Skeggs .tidy = gk20a_clk_tidy,
6036625f55cSBen Skeggs .pstates = gk20a_pstates,
6046625f55cSBen Skeggs .nr_pstates = ARRAY_SIZE(gk20a_pstates),
6056625f55cSBen Skeggs .domains = {
6066625f55cSBen Skeggs { nv_clk_src_crystal, 0xff },
6076625f55cSBen Skeggs { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
6086625f55cSBen Skeggs { nv_clk_src_max }
6096625f55cSBen Skeggs }
6106625f55cSBen Skeggs };
6116625f55cSBen Skeggs
6126625f55cSBen Skeggs int
gk20a_clk_ctor(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,const struct nvkm_clk_func * func,const struct gk20a_clk_pllg_params * params,struct gk20a_clk * clk)613*98fd7f83SBen Skeggs gk20a_clk_ctor(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
614*98fd7f83SBen Skeggs const struct nvkm_clk_func *func, const struct gk20a_clk_pllg_params *params,
6152efd3908SAlexandre Courbot struct gk20a_clk *clk)
616f3867f43SBen Skeggs {
61743a70661SBen Skeggs struct nvkm_device_tegra *tdev = device->func->tegra(device);
6182efd3908SAlexandre Courbot int ret;
6192efd3908SAlexandre Courbot int i;
6206625f55cSBen Skeggs
6212efd3908SAlexandre Courbot /* Finish initializing the pstates */
6222efd3908SAlexandre Courbot for (i = 0; i < func->nr_pstates; i++) {
6232efd3908SAlexandre Courbot INIT_LIST_HEAD(&func->pstates[i].list);
6242efd3908SAlexandre Courbot func->pstates[i].pstate = i + 1;
6252efd3908SAlexandre Courbot }
6262efd3908SAlexandre Courbot
6272efd3908SAlexandre Courbot clk->params = params;
6282efd3908SAlexandre Courbot clk->parent_rate = clk_get_rate(tdev->clk);
6292efd3908SAlexandre Courbot
630*98fd7f83SBen Skeggs ret = nvkm_clk_ctor(func, device, type, inst, true, &clk->base);
6312efd3908SAlexandre Courbot if (ret)
6322efd3908SAlexandre Courbot return ret;
6332efd3908SAlexandre Courbot
6342efd3908SAlexandre Courbot nvkm_debug(&clk->base.subdev, "parent clock rate: %d Khz\n",
6352efd3908SAlexandre Courbot clk->parent_rate / KHZ);
6362efd3908SAlexandre Courbot
6372efd3908SAlexandre Courbot return 0;
6382efd3908SAlexandre Courbot }
6392efd3908SAlexandre Courbot
6402efd3908SAlexandre Courbot int
gk20a_clk_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_clk ** pclk)641*98fd7f83SBen Skeggs gk20a_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
642*98fd7f83SBen Skeggs struct nvkm_clk **pclk)
6432efd3908SAlexandre Courbot {
6442efd3908SAlexandre Courbot struct gk20a_clk *clk;
6452efd3908SAlexandre Courbot int ret;
6462efd3908SAlexandre Courbot
6472efd3908SAlexandre Courbot clk = kzalloc(sizeof(*clk), GFP_KERNEL);
6482efd3908SAlexandre Courbot if (!clk)
6496625f55cSBen Skeggs return -ENOMEM;
6506625f55cSBen Skeggs *pclk = &clk->base;
651f3867f43SBen Skeggs
652*98fd7f83SBen Skeggs ret = gk20a_clk_ctor(device, type, inst, &gk20a_clk, &gk20a_pllg_params, clk);
653195c1137SAlexandre Courbot
654195c1137SAlexandre Courbot clk->pl_to_div = pl_to_div;
655195c1137SAlexandre Courbot clk->div_to_pl = div_to_pl;
6566625f55cSBen Skeggs return ret;
657f3867f43SBen Skeggs }
658