1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (C) 2005-2008 Texas Instruments, Inc.
6  * Copyright (C) 2004-2010 Nokia Corporation
9  * Richard Woodruff <r-woodruff2@ti.com>
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
19 #include <linux/clk/ti.h>
25 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
30 #define DPLL_MULT_UNDERFLOW		-1
51 #define DPLL_FINT_UNDERFLOW		-1
52 #define DPLL_FINT_INVALID		-2
57  * _dpll_test_fint - test whether an Fint value is valid for the DPLL
58  * @clk: DPLL struct clk to test
59  * @n: divider value (N) to test
61  * Tests whether a particular divider @n will result in a valid DPLL
63  * Correction".  Returns 0 if OK, -1 if the enclosing loop can terminate
64  * (assuming that it is counting N upwards), or -2 if the enclosing loop
67 static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n)  in _dpll_test_fint()  argument
73 	dd = clk->dpll_data;  in _dpll_test_fint()
75 	/* DPLL divider must result in a valid jitter correction val */  in _dpll_test_fint()
76 	fint = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)) / n;  in _dpll_test_fint()
78 	if (dd->flags & DPLL_J_TYPE) {  in _dpll_test_fint()
82 		fint_min = ti_clk_get_features()->fint_min;  in _dpll_test_fint()
83 		fint_max = ti_clk_get_features()->fint_max;  in _dpll_test_fint()
91 	if (fint < ti_clk_get_features()->fint_min) {  in _dpll_test_fint()
94 		dd->max_divider = n;  in _dpll_test_fint()
96 	} else if (fint > ti_clk_get_features()->fint_max) {  in _dpll_test_fint()
99 		dd->min_divider = n;  in _dpll_test_fint()
101 	} else if (fint > ti_clk_get_features()->fint_band1_max &&  in _dpll_test_fint()
102 		   fint < ti_clk_get_features()->fint_band2_min) {  in _dpll_test_fint()
121  * _dpll_test_mult - test a DPLL multiplier value
123  * @n: current DPLL n (divider) value under test
133  * a non-scaled m upon return.  This non-scaled m will result in a
137  * non-scaled m attempted to underflow, which can allow the calling
157 		(*m)--;  in _dpll_test_mult()
175  * _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not
179  * mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise.
185 	mask = ti_clk_get_features()->dpll_bypass_vals;  in _omap2_dpll_is_in_bypass()
189 	 * to the bitshift. Go through each set-bit in the mask and  in _omap2_dpll_is_in_bypass()
205 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);  in omap2_init_dpll_parent()  local
209 	dd = clk->dpll_data;  in omap2_init_dpll_parent()
211 		return -EINVAL;  in omap2_init_dpll_parent()
213 	v = ti_clk_ll_ops->clk_readl(&dd->control_reg);  in omap2_init_dpll_parent()
214 	v &= dd->enable_mask;  in omap2_init_dpll_parent()
215 	v >>= __ffs(dd->enable_mask);  in omap2_init_dpll_parent()
217 	/* Reparent the struct clk in case the dpll is in bypass */  in omap2_init_dpll_parent()
225  * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
226  * @clk: struct clk * of a DPLL
228  * DPLLs can be locked or bypassed - basically, enabled or disabled.
236  * if the clock @clk is not a DPLL.
238 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)  in omap2_get_dpll_rate()  argument
244 	dd = clk->dpll_data;  in omap2_get_dpll_rate()
249 	v = ti_clk_ll_ops->clk_readl(&dd->control_reg);  in omap2_get_dpll_rate()
250 	v &= dd->enable_mask;  in omap2_get_dpll_rate()
251 	v >>= __ffs(dd->enable_mask);  in omap2_get_dpll_rate()
254 		return clk_hw_get_rate(dd->clk_bypass);  in omap2_get_dpll_rate()
256 	v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);  in omap2_get_dpll_rate()
257 	dpll_mult = v & dd->mult_mask;  in omap2_get_dpll_rate()
258 	dpll_mult >>= __ffs(dd->mult_mask);  in omap2_get_dpll_rate()
259 	dpll_div = v & dd->div1_mask;  in omap2_get_dpll_rate()
260 	dpll_div >>= __ffs(dd->div1_mask);  in omap2_get_dpll_rate()
262 	dpll_clk = (u64)clk_hw_get_rate(dd->clk_ref) * dpll_mult;  in omap2_get_dpll_rate()
271  * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
272  * @hw: struct clk_hw containing the struct clk * for a DPLL
286 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);  in omap2_dpll_round_rate()  local
297 	if (!clk || !clk->dpll_data)  in omap2_dpll_round_rate()
300 	dd = clk->dpll_data;  in omap2_dpll_round_rate()
302 	if (dd->max_rate && target_rate > dd->max_rate)  in omap2_dpll_round_rate()
303 		target_rate = dd->max_rate;  in omap2_dpll_round_rate()
305 	ref_rate = clk_hw_get_rate(dd->clk_ref);  in omap2_dpll_round_rate()
311 	scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;  in omap2_dpll_round_rate()
313 	dd->last_rounded_rate = 0;  in omap2_dpll_round_rate()
315 	for (n = dd->min_divider; n <= dd->max_divider; n++) {  in omap2_dpll_round_rate()
316 		/* Is the (input clk, divider) pair valid for the DPLL? */  in omap2_dpll_round_rate()
317 		r = _dpll_test_fint(clk, n);  in omap2_dpll_round_rate()
323 		/* Compute the scaled DPLL multiplier, based on the divider */  in omap2_dpll_round_rate()
338 		/* m can't be set low enough for this n - try with a larger n */  in omap2_dpll_round_rate()
343 		delta = target_rate - new_rate;  in omap2_dpll_round_rate()
366 	dd->last_rounded_m = min_delta_m;  in omap2_dpll_round_rate()
367 	dd->last_rounded_n = min_delta_n;  in omap2_dpll_round_rate()
368 	dd->last_rounded_rate = target_rate - prev_min_delta;  in omap2_dpll_round_rate()
370 	return dd->last_rounded_rate;  in omap2_dpll_round_rate()