Lines Matching +full:clk +full:- +full:divider +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0+
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 #include <linux/clk.h>
24 #include "cpufreq-dt.h"
26 /* Clk register set */
69 * divider, a VDD level, etc...
100 u8 divider[LOAD_LEVEL_NR];
105 {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} },
106 {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
107 {.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} },
108 {.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} },
129 struct regmap *clk_base, u8 *divider)
162 * Set cpu divider based on the pre-computed array in
165 val |= divider[load_lvl] << ARMADA_37XX_NB_TBG_DIV_OFF;
169 /* Set VDD divider which is actually the load level. */
183 * the round-up closest to the target voltage value.
189 /* Find out the round-up closest supported voltage value */
199 avs = ARRAY_SIZE(avs_map) - 1;
207 * - L0 can be read out from the register of AVS_CTRL_0 and L0 voltage
209 * - L1 voltage should be about 100mv smaller than L0 voltage
210 * - L2 & L3 voltage should be about 150mv smaller than L0 voltage.
234 dvfs->avs[0] = l0_vdd_min;
244 dvfs->avs[load_level] = avs_min;
251 if (dvfs->cpu_freq_max >= 1000*1000*1000) {
252 if (dvfs->cpu_freq_max >= 1200*1000*1000)
256 dvfs->avs[0] = dvfs->avs[1] = avs_min;
263 * L1 voltage is equal to L0 voltage - 100mv and it must be
267 target_vm = avs_map[l0_vdd_min] - 100;
269 dvfs->avs[1] = armada_37xx_avs_val_match(target_vm);
272 * L2 & L3 voltage is equal to L0 voltage - 150mv and it must
275 target_vm = avs_map[l0_vdd_min] - 150;
277 dvfs->avs[2] = dvfs->avs[3] = armada_37xx_avs_val_match(target_vm);
284 if (dvfs->cpu_freq_max >= 1000*1000*1000) {
287 if (dvfs->cpu_freq_max >= 1200*1000*1000)
292 if (avs_min_l1 > dvfs->avs[0])
293 avs_min_l1 = dvfs->avs[0];
295 if (dvfs->avs[1] < avs_min_l1)
296 dvfs->avs[1] = avs_min_l1;
314 /* Enable low voltage mode */
321 avs_val = dvfs->avs[load_level];
322 regmap_update_bits(base, ARMADA_37XX_AVS_VSET(load_level-1),
366 regmap_read(state->regmap, ARMADA_37XX_NB_L0L1, &state->nb_l0l1);
367 regmap_read(state->regmap, ARMADA_37XX_NB_L2L3, &state->nb_l2l3);
368 regmap_read(state->regmap, ARMADA_37XX_NB_CPU_LOAD,
369 &state->nb_cpu_load);
370 regmap_read(state->regmap, ARMADA_37XX_NB_DYN_MOD, &state->nb_dyn_mod);
380 armada37xx_cpufreq_disable_dvfs(state->regmap);
382 regmap_write(state->regmap, ARMADA_37XX_NB_L0L1, state->nb_l0l1);
383 regmap_write(state->regmap, ARMADA_37XX_NB_L2L3, state->nb_l2l3);
384 regmap_write(state->regmap, ARMADA_37XX_NB_CPU_LOAD,
385 state->nb_cpu_load);
392 regmap_write(state->regmap, ARMADA_37XX_NB_DYN_MOD, state->nb_dyn_mod);
407 struct clk *clk, *parent;
410 syscon_regmap_lookup_by_compatible("marvell,armada-3700-periph-clock-nb");
412 return -ENODEV;
415 syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
418 return -ENODEV;
421 syscon_regmap_lookup_by_compatible("marvell,armada-3700-avs");
439 return -ENODEV;
442 clk = clk_get(cpu_dev, NULL);
443 if (IS_ERR(clk)) {
445 return PTR_ERR(clk);
448 parent = clk_get_parent(clk);
451 clk_put(clk);
460 clk_put(clk);
461 return -EINVAL;
466 clk_put(clk);
467 return -EINVAL;
473 clk_put(clk);
474 return -ENOMEM;
477 armada37xx_cpufreq_state->regmap = nb_pm_base;
482 armada37xx_cpufreq_dvfs_setup(nb_pm_base, nb_clk_base, dvfs->divider);
483 clk_put(clk);
487 unsigned long u_volt = avs_map[dvfs->avs[load_lvl]] * 1000;
488 freq = base_frequency / dvfs->divider[load_lvl];
503 pdev = platform_device_register_data(NULL, "cpufreq-dt", -1, &pdata,
509 armada37xx_cpufreq_state->cpu_dev = cpu_dev;
510 armada37xx_cpufreq_state->pdev = pdev;
517 /* clean-up the already added opp before leaving */
518 while (load_lvl-- > ARMADA_37XX_DVFS_LOAD_0) {
519 freq = base_frequency / dvfs->divider[load_lvl];
532 struct platform_device *pdev = armada37xx_cpufreq_state->pdev;
539 armada37xx_cpufreq_disable_dvfs(armada37xx_cpufreq_state->regmap);
542 freq = dvfs->cpu_freq_max / dvfs->divider[load_lvl];
543 dev_pm_opp_remove(armada37xx_cpufreq_state->cpu_dev, freq);
551 { .compatible = "marvell,armada-3700-nb-pm" },
556 MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");