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/freebsd/sys/dev/clk/allwinner/
H A Daw_clk_prediv_mux.c1 /*-
30 #include <dev/clk/clk.h>
32 #include <dev/clk/allwinner/aw_clk.h>
33 #include <dev/clk/allwinner/aw_clk_prediv_mux.h>
40 * clk = clkin / prediv / div
52 struct aw_clk_factor div; member
70 aw_clk_prediv_mux_init(struct clknode *clk, device_t dev) in aw_clk_prediv_mux_init() argument
75 sc = clknode_get_softc(clk); in aw_clk_prediv_mux_init()
77 DEVICE_LOCK(clk); in aw_clk_prediv_mux_init()
78 READ4(clk, sc->offset, &val); in aw_clk_prediv_mux_init()
[all …]
H A Dccu_de2.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
45 #include <dev/clk/clk_div.h>
46 #include <dev/clk/clk_fixed.h>
47 #include <dev/clk/clk_mux.h>
51 #include <dev/clk/allwinner/aw_ccung.h>
53 #include <dt-bindings/clock/sun8i-de2.h>
54 #include <dt-bindings/reset/sun8i-de2.h>
78 CCU_GATE(CLK_BUS_MIXER0, "mixer0", "mixer0-div", 0x00, 0)
79 CCU_GATE(CLK_BUS_WB, "wb", "wb-div", 0x00, 2)
[all …]
H A Dccu_a64.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
41 #include <dev/clk/clk_div.h>
42 #include <dev/clk/clk_fixed.h>
43 #include <dev/clk/clk_mux.h>
45 #include <dev/clk/allwinner/aw_ccung.h>
47 #include <dt-bindings/clock/sun50i-a64-ccu.h>
48 #include <dt-bindings/reset/sun50i-a64-ccu.h>
50 /* Non-exported clocks */
141 CCU_GATE(CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 0x60, 1)
[all …]
H A Dccu_sun8i_r.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
45 #include <dev/clk/clk_div.h>
46 #include <dev/clk/clk_fixed.h>
47 #include <dev/clk/clk_mux.h>
49 #include <dev/clk/allwinner/aw_ccung.h>
51 #include <dt-bindings/clock/sun8i-r-ccu.h>
52 #include <dt-bindings/reset/sun8i-r-ccu.h>
54 /* Non-exported clocks */
67 CCU_GATE(CLK_APB0_PIO, "apb0-pio", "apb0", 0x28, 0)
[all …]
H A Dccu_h6_r.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
41 #include <dev/clk/clk_div.h>
42 #include <dev/clk/clk_fixed.h>
43 #include <dev/clk/clk_mux.h>
45 #include <dev/clk/allwinner/aw_ccung.h>
47 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
48 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
50 /* Non-exported clocks */
65 CCU_GATE(CLK_R_APB1_TIMER, "r_apb1-timer", "r_apb1", 0x11c, 0)
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/freebsd/sys/contrib/device-tree/src/mips/mobileye/
H A Deyeq5-clocks.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
6 #include <dt-bindings/clock/mobileye,eyeq5-clk.h>
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <30000000>;
17 occ_cpu: occ-cpu {
18 compatible = "fixed-factor-clock";
20 #clock-cells = <0>;
21 clock-div = <1>;
22 clock-mult = <1>;
[all …]
H A Deyeq5-fixed-clocks.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 pll_cpu: pll-cpu {
9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <1500000000>;
14 pll_vdi: pll-vdi {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <1280000000>;
20 pll_per: pll-per {
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/freebsd/sys/dev/clk/rockchip/
H A Drk_clk_composite.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
32 #include <dev/clk/clk.h>
35 #include <dev/clk/rockchip/rk_clk_composite.h>
68 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg)
74 rk_clk_composite_read_4(struct clknode *clk, bus_addr_t addr, uint32_t *val) in rk_clk_composite_read_4() argument
78 sc = clknode_get_softc(clk); in rk_clk_composite_read_4()
79 if (sc->grf) in rk_clk_composite_read_4()
80 *val = SYSCON_READ_4(sc->grf, addr); in rk_clk_composite_read_4()
82 CLKDEV_READ_4(clknode_get_device(clk), addr, val); in rk_clk_composite_read_4()
[all …]
H A Drk_clk_armclk.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
32 #include <dev/clk/clk.h>
34 #include <dev/clk/rockchip/rk_clk_armclk.h>
73 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg)
79 rk_clk_armclk_init(struct clknode *clk, device_t dev) in rk_clk_armclk_init() argument
84 sc = clknode_get_softc(clk); in rk_clk_armclk_init()
87 DEVICE_LOCK(clk); in rk_clk_armclk_init()
88 READ4(clk, sc->muxdiv_offset, &val); in rk_clk_armclk_init()
89 DEVICE_UNLOCK(clk); in rk_clk_armclk_init()
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/freebsd/sys/dev/clk/xilinx/
H A Dzynqmp_clk_div.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
34 #include <dev/clk/clk.h>
36 #include <dev/clk/xilinx/zynqmp_clk_div.h>
50 zynqmp_clk_div_init(struct clknode *clk, device_t dev) in zynqmp_clk_div_init() argument
53 clknode_init_parent_idx(clk, 0); in zynqmp_clk_div_init()
58 zynqmp_clk_div_recalc(struct clknode *clk, uint64_t *freq) in zynqmp_clk_div_recalc() argument
61 uint32_t div; in zynqmp_clk_div_recalc() local
64 sc = clknode_get_softc(clk); in zynqmp_clk_div_recalc()
65 rv = ZYNQMP_FIRMWARE_CLOCK_GETDIVIDER(sc->firmware, sc->id, &div); in zynqmp_clk_div_recalc()
[all …]
H A Dzynqmp_clk_fixed.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
34 #include <dev/clk/clk.h>
36 #include <dev/clk/xilinx/zynqmp_clk_fixed.h>
47 zynqmp_clk_fixed_init(struct clknode *clk, device_t dev) in zynqmp_clk_fixed_init() argument
50 clknode_init_parent_idx(clk, 0); in zynqmp_clk_fixed_init()
55 zynqmp_clk_fixed_recalc(struct clknode *clk, uint64_t *freq) in zynqmp_clk_fixed_recalc() argument
58 uint32_t mult, div; in zynqmp_clk_fixed_recalc() local
61 sc = clknode_get_softc(clk); in zynqmp_clk_fixed_recalc()
62 rv = ZYNQMP_FIRMWARE_CLOCK_GET_FIXEDFACTOR(sc->firmware, sc->id, &mult, &div); in zynqmp_clk_fixed_recalc()
[all …]
H A Dzynqmp_clk_pll.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
34 #include <dev/clk/clk.h>
36 #include <dev/clk/xilinx/zynqmp_clk_pll.h>
53 zynqmp_clk_pll_init(struct clknode *clk, device_t dev) in zynqmp_clk_pll_init() argument
56 clknode_init_parent_idx(clk, 0); in zynqmp_clk_pll_init()
61 zynqmp_clk_pll_recalc(struct clknode *clk, uint64_t *freq) in zynqmp_clk_pll_recalc() argument
65 uint32_t div, mode, frac; in zynqmp_clk_pll_recalc() local
68 sc = clknode_get_softc(clk); in zynqmp_clk_pll_recalc()
69 rv = ZYNQMP_FIRMWARE_CLOCK_GETDIVIDER(sc->firmware, sc->id, &div); in zynqmp_clk_pll_recalc()
[all …]
/freebsd/sys/dev/qcom_clk/
H A Dqcom_clk_ro_div.c1 /*-
34 #include <dev/clk/clk.h>
35 #include <dev/clk/clk_div.h>
36 #include <dev/clk/clk_fixed.h>
37 #include <dev/clk/clk_mux.h>
50 * This is a read-only divisor table node.
54 * It likely should just live in the extres/clk code.
66 qcom_clk_ro_div_recalc(struct clknode *clk, uint64_t *freq) in qcom_clk_ro_div_recalc() argument
69 uint32_t reg, idx, div = 1; in qcom_clk_ro_div_recalc() local
72 sc = clknode_get_softc(clk); in qcom_clk_ro_div_recalc()
[all …]
/freebsd/sys/dev/clk/
H A Dclk_fixed.c1 /*-
47 #include <dev/clk/clk_fixed.h>
52 static int clknode_fixed_init(struct clknode *clk, device_t dev);
53 static int clknode_fixed_recalc(struct clknode *clk, uint64_t *freq);
54 static int clknode_fixed_set_freq(struct clknode *clk, uint64_t fin,
61 uint32_t div; member
75 clknode_fixed_init(struct clknode *clk, device_t dev) in clknode_fixed_init() argument
79 sc = clknode_get_softc(clk); in clknode_fixed_init()
80 if (sc->freq == 0) in clknode_fixed_init()
81 clknode_init_parent_idx(clk, 0); in clknode_fixed_init()
[all …]
/freebsd/sys/arm64/freescale/imx/clk/
H A Dimx_clk_frac_pll.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
32 #include <dev/clk/clk.h>
34 #include <arm64/freescale/imx/clk/imx_clk_frac_pll.h>
67 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg)
73 imx_clk_frac_pll_init(struct clknode *clk, device_t dev) in imx_clk_frac_pll_init() argument
76 clknode_init_parent_idx(clk, 0); in imx_clk_frac_pll_init()
81 imx_clk_frac_pll_set_gate(struct clknode *clk, bool enable) in imx_clk_frac_pll_set_gate() argument
87 sc = clknode_get_softc(clk); in imx_clk_frac_pll_set_gate()
89 DEVICE_LOCK(clk); in imx_clk_frac_pll_set_gate()
[all …]
H A Dimx_clk_sscg_pll.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
32 #include <dev/clk/clk.h>
34 #include <arm64/freescale/imx/clk/imx_clk_sscg_pll.h>
71 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg)
77 imx_clk_sscg_pll_init(struct clknode *clk, device_t dev) in imx_clk_sscg_pll_init() argument
79 if (clknode_get_parents_num(clk) > 1) { in imx_clk_sscg_pll_init()
80 device_printf(clknode_get_device(clk), in imx_clk_sscg_pll_init()
84 clknode_init_parent_idx(clk, 0); in imx_clk_sscg_pll_init()
90 imx_clk_sscg_pll_set_gate(struct clknode *clk, bool enable) in imx_clk_sscg_pll_set_gate() argument
[all …]
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Dnvidia,tegra20-i2c.txt4 - compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or
5 "nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c".
6 For Tegra114, must be "nvidia,tegra114-i2c". Otherwise, must be
7 "nvidia,<chip>-i2c", plus at least one of the above, where <chip> is
10 nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C
14 "nvidia,tegra20-i2c-dvc".
15 nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support
16 master and slave mode of I2C communication. The i2c-tegra driver only
18 only compatible with "nvidia,tegra20-i2c".
19 nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is
[all …]
H A Dnvidia,tegra20-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Thierry Reding <thierry.reding@gmail.com>
9 - Jon Hunter <jonathanh@nvidia.com>
16 - description: Tegra20 has 4 generic I2C controller. This can support
17 master and slave mode of I2C communication. The i2c-tegra driver
19 controller is only compatible with "nvidia,tegra20-i2c".
20 const: nvidia,tegra20-i2c
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Damlogic,c3-peripherals-clkc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
4 ---
5 $id: http://devicetree.org/schemas/clock/amlogic,c3-peripherals-clkc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
12 - Jerome Brunet <jbrunet@baylibre.com>
13 - Xianwei Zhao <xianwei.zhao@amlogic.com>
14 - Chuan Liu <chuan.liu@amlogic.com>
18 const: amlogic,c3-peripherals-clkc
[all …]
/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-metho
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/freebsd/sys/arm/mv/clk/
H A Dperiph_clk_d.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
38 #include <dev/clk/clk.h>
39 #include <dev/clk/clk_div.h>
40 #include <dev/clk/clk_fixed.h>
41 #include <dev/clk/clk_gate.h>
42 #include <dev/clk/clk_mux.h>
53 * Register chain: mux (select proper TBG) -> div1 (first frequency divider) ->
54 * div2 (second frequency divider) -> mux (select divided freq.
55 * or xtal output) -> gate (enable or disable clock), which is also final node
[all …]
H A Dperiph.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
38 #include <dev/clk/clk.h>
39 #include <dev/clk/clk_div.h>
40 #include <dev/clk/clk_fixed.h>
41 #include <dev/clk/clk_gate.h>
42 #include <dev/clk/clk_mux.h>
56 mux->clkdef.id = id; in a37x0_periph_create_mux()
60 printf("Failed to create %s: %d\n", mux->clkdef.name, error); in a37x0_periph_create_mux()
69 struct clk_div_def *div, int id) in a37x0_periph_create_div() argument
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
23 #clock-cells = <0>;
[all …]
H A Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
25 #clock-cells = <0>;
[all …]
/freebsd/sys/arm64/freescale/imx/
H A Dimx_ccm.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
31 #include <dev/clk/clk.h>
32 #include <dev/clk/clk_div.h>
33 #include <dev/clk/clk_fixed.h>
34 #include <dev/clk/clk_gate.h>
35 #include <dev/clk/clk_link.h>
73 struct clk_div_def *div; member
74 } clk; member
81 .clk.link = &(struct clk_link_def) { \
[all …]

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