1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2017,2018 Emmanuel Vadot <manu@freebsd.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/bus.h>
31 #include <sys/rman.h>
32 #include <sys/kernel.h>
33 #include <sys/module.h>
34 #include <machine/bus.h>
35
36 #include <dev/fdt/simplebus.h>
37
38 #include <dev/ofw/ofw_bus.h>
39 #include <dev/ofw/ofw_bus_subr.h>
40
41 #if defined(__aarch64__)
42 #include "opt_soc.h"
43 #endif
44
45 #include <dev/clk/clk_div.h>
46 #include <dev/clk/clk_fixed.h>
47 #include <dev/clk/clk_mux.h>
48
49 #include <dev/clk/allwinner/aw_ccung.h>
50
51 #include <dt-bindings/clock/sun8i-r-ccu.h>
52 #include <dt-bindings/reset/sun8i-r-ccu.h>
53
54 /* Non-exported clocks */
55 #define CLK_AHB0 1
56 #define CLK_APB0 2
57
58 static struct aw_ccung_reset ccu_sun8i_r_resets[] = {
59 CCU_RESET(RST_APB0_IR, 0xb0, 1)
60 CCU_RESET(RST_APB0_TIMER, 0xb0, 2)
61 CCU_RESET(RST_APB0_RSB, 0xb0, 3)
62 CCU_RESET(RST_APB0_UART, 0xb0, 4)
63 CCU_RESET(RST_APB0_I2C, 0xb0, 6)
64 };
65
66 static struct aw_ccung_gate ccu_sun8i_r_gates[] = {
67 CCU_GATE(CLK_APB0_PIO, "apb0-pio", "apb0", 0x28, 0)
68 CCU_GATE(CLK_APB0_IR, "apb0-ir", "apb0", 0x28, 1)
69 CCU_GATE(CLK_APB0_TIMER, "apb0-timer", "apb0", 0x28, 2)
70 CCU_GATE(CLK_APB0_RSB, "apb0-rsb", "apb0", 0x28, 3)
71 CCU_GATE(CLK_APB0_UART, "apb0-uart", "apb0", 0x28, 4)
72 CCU_GATE(CLK_APB0_I2C, "apb0-i2c", "apb0", 0x28, 6)
73 CCU_GATE(CLK_APB0_TWD, "apb0-twd", "apb0", 0x28, 7)
74 };
75
76 static const char *ar100_parents[] = {"osc32k", "osc24M", "pll_periph0", "iosc"};
77 static const char *a83t_ar100_parents[] = {"osc16M-d512", "osc24M", "pll_periph", "osc16M"};
78 PREDIV_CLK(ar100_clk, CLK_AR100, /* id */
79 "ar100", ar100_parents, /* name, parents */
80 0x00, /* offset */
81 16, 2, /* mux */
82 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */
83 8, 5, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */
84 16, 2, 2); /* prediv condition */
85 PREDIV_CLK(a83t_ar100_clk, CLK_AR100, /* id */
86 "ar100", a83t_ar100_parents, /* name, parents */
87 0x00, /* offset */
88 16, 2, /* mux */
89 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */
90 8, 5, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */
91 16, 2, 2); /* prediv condition */
92
93 static const char *ahb0_parents[] = {"ar100"};
94 FIXED_CLK(ahb0_clk,
95 CLK_AHB0, /* id */
96 "ahb0", /* name */
97 ahb0_parents, /* parent */
98 0, /* freq */
99 1, /* mult */
100 1, /* div */
101 0); /* flags */
102
103 static const char *apb0_parents[] = {"ahb0"};
104 DIV_CLK(apb0_clk,
105 CLK_APB0, /* id */
106 "apb0", apb0_parents, /* name, parents */
107 0x0c, /* offset */
108 0, 2, /* shift, width */
109 0, NULL); /* flags, div table */
110
111 static const char *r_ccu_ir_parents[] = {"osc32k", "osc24M"};
112 NM_CLK(r_ccu_ir_clk,
113 CLK_IR, /* id */
114 "ir", r_ccu_ir_parents, /* names, parents */
115 0x54, /* offset */
116 0, 4, 0, 0, /* N factor */
117 16, 2, 0, 0, /* M factor */
118 24, 2, /* mux */
119 31, /* gate */
120 AW_CLK_HAS_MUX | AW_CLK_REPARENT | AW_CLK_HAS_GATE);/* flags */
121
122 static const char *a83t_ir_parents[] = {"osc16M", "osc24M"};
123 static struct aw_clk_nm_def a83t_ir_clk = {
124 .clkdef = {
125 .id = CLK_IR,
126 .name = "ir",
127 .parent_names = a83t_ir_parents,
128 .parent_cnt = nitems(a83t_ir_parents),
129 },
130 .offset = 0x54,
131 .n = {.shift = 0, .width = 4, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
132 .m = {.shift = 16, .width = 2},
133 .prediv = {
134 .cond_shift = 24,
135 .cond_width = 2,
136 .cond_value = 0,
137 .value = 16
138 },
139 .mux_shift = 24,
140 .mux_width = 2,
141 .flags = AW_CLK_HAS_MUX | AW_CLK_HAS_PREDIV,
142 };
143
144 static struct aw_ccung_clk clks[] = {
145 { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ar100_clk},
146 { .type = AW_CLK_DIV, .clk.div = &apb0_clk},
147 { .type = AW_CLK_FIXED, .clk.fixed = &ahb0_clk},
148 { .type = AW_CLK_NM, .clk.nm = &r_ccu_ir_clk},
149 };
150
151 static struct aw_ccung_clk a83t_clks[] = {
152 { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &a83t_ar100_clk},
153 { .type = AW_CLK_DIV, .clk.div = &apb0_clk},
154 { .type = AW_CLK_FIXED, .clk.fixed = &ahb0_clk},
155 { .type = AW_CLK_NM, .clk.nm = &a83t_ir_clk},
156 };
157
158 static struct ofw_compat_data compat_data[] = {
159 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5)
160 { "allwinner,sun8i-h3-r-ccu", 1 },
161 #endif
162 #if defined(SOC_ALLWINNER_A64)
163 { "allwinner,sun50i-a64-r-ccu", 1 },
164 #endif
165 { NULL, 0},
166 };
167
168 static int
ccu_sun8i_r_probe(device_t dev)169 ccu_sun8i_r_probe(device_t dev)
170 {
171
172 if (!ofw_bus_status_okay(dev))
173 return (ENXIO);
174
175 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
176 return (ENXIO);
177
178 device_set_desc(dev, "Allwinner SUN8I_R Clock Control Unit NG");
179 return (BUS_PROBE_DEFAULT);
180 }
181
182 static int
ccu_sun8i_r_attach(device_t dev)183 ccu_sun8i_r_attach(device_t dev)
184 {
185 struct aw_ccung_softc *sc;
186
187 sc = device_get_softc(dev);
188
189 sc->resets = ccu_sun8i_r_resets;
190 sc->nresets = nitems(ccu_sun8i_r_resets);
191 sc->gates = ccu_sun8i_r_gates;
192 sc->ngates = nitems(ccu_sun8i_r_gates);
193 sc->clks = clks;
194 sc->nclks = nitems(clks);
195
196 return (aw_ccung_attach(dev));
197 }
198
199 static device_method_t ccu_sun8i_r_methods[] = {
200 /* Device interface */
201 DEVMETHOD(device_probe, ccu_sun8i_r_probe),
202 DEVMETHOD(device_attach, ccu_sun8i_r_attach),
203
204 DEVMETHOD_END
205 };
206
207 DEFINE_CLASS_1(ccu_sun8i_r, ccu_sun8i_r_driver, ccu_sun8i_r_methods,
208 sizeof(struct aw_ccung_softc), aw_ccung_driver);
209
210 EARLY_DRIVER_MODULE(ccu_sun8i_r, simplebus, ccu_sun8i_r_driver, 0, 0,
211 BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
212
213 static int
ccu_a83t_r_probe(device_t dev)214 ccu_a83t_r_probe(device_t dev)
215 {
216
217 if (!ofw_bus_status_okay(dev))
218 return (ENXIO);
219
220 if (!ofw_bus_is_compatible(dev, "allwinner,sun8i-a83t-r-ccu"))
221 return (ENXIO);
222
223 device_set_desc(dev, "Allwinner A83T_R Clock Control Unit NG");
224 return (BUS_PROBE_DEFAULT);
225 }
226
227 static int
ccu_a83t_r_attach(device_t dev)228 ccu_a83t_r_attach(device_t dev)
229 {
230 struct aw_ccung_softc *sc;
231
232 sc = device_get_softc(dev);
233
234 sc->resets = ccu_sun8i_r_resets;
235 sc->nresets = nitems(ccu_sun8i_r_resets);
236 sc->gates = ccu_sun8i_r_gates;
237 sc->ngates = nitems(ccu_sun8i_r_gates);
238 sc->clks = a83t_clks;
239 sc->nclks = nitems(a83t_clks);
240
241 return (aw_ccung_attach(dev));
242 }
243
244 static device_method_t ccu_a83t_r_methods[] = {
245 /* Device interface */
246 DEVMETHOD(device_probe, ccu_a83t_r_probe),
247 DEVMETHOD(device_attach, ccu_a83t_r_attach),
248
249 DEVMETHOD_END
250 };
251
252 DEFINE_CLASS_1(ccu_a83t_r, ccu_a83t_r_driver, ccu_a83t_r_methods,
253 sizeof(struct aw_ccung_softc), aw_ccung_driver);
254
255 EARLY_DRIVER_MODULE(ccu_a83t_r, simplebus, ccu_a83t_r_driver, 0, 0,
256 BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
257