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/linux/Documentation/userspace-api/media/cec/
H A Dcec-pin-error-inj.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
9 has low-level support for the CEC bus. Most hardware today will have
10 high-level CEC support where the hardware deals with driving the CEC bus,
19 Currently only the cec-gpio driver (when the CEC line is directly
20 connected to a pull-up GPIO line) and the AllWinner A10/A20 drm driver
25 now an ``error-inj`` file.
32 With ``cat error-inj`` you can see both the possible commands and the current
35 $ cat /sys/kernel/debug/cec/cec0/error-inj
36 # Clear error injections:
37 # clear clear all rx and tx error injections
[all …]
/linux/include/linux/amba/
H A Dserial.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/include/asm-arm/hardware/serial_amba.h
20 /* -------------------------------------------------------------------------------
22 * -------------------------------------------------------------------------------
27 #define UART01x_ECR 0x04 /* Error clear register (Write). */
36 #define UART010_ICR 0x1C /* Interrupt clear register (Write). */
48 #define UART011_ICR 0x44 /* Interrupt clear register. */
58 #define ST_UART011_ABIMSC 0x15C /* Autobaud interrupt mask/clear register. */
78 #define UART011_DR_OE BIT(11)
79 #define UART011_DR_BE BIT(10)
[all …]
/linux/drivers/media/cec/core/
H A Dcec-pin-error-inj.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <media/cec-pin.h>
11 #include "cec-pin-priv.h"
20 { CEC_ERROR_INJ_RX_NACK_OFFSET, -1, "rx-nack" },
22 CEC_ERROR_INJ_RX_LOW_DRIVE_ARG_IDX, "rx-low-drive" },
23 { CEC_ERROR_INJ_RX_ADD_BYTE_OFFSET, -1, "rx-add-byte" },
24 { CEC_ERROR_INJ_RX_REMOVE_BYTE_OFFSET, -1, "rx-remove-byte" },
26 CEC_ERROR_INJ_RX_ARB_LOST_ARG_IDX, "rx-arb-lost" },
28 { CEC_ERROR_INJ_TX_NO_EOM_OFFSET, -1, "tx-no-eom" },
29 { CEC_ERROR_INJ_TX_EARLY_EOM_OFFSET, -1, "tx-early-eom" },
[all …]
/linux/include/uapi/linux/
H A Dpps.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
5 * Copyright (C) 2005-2009 Rodolfo Giometti <giometti@linux.it>
31 /* Implementation note: the logical states ``assert'' and ``clear''
33 * means the bit is set. */
43 /* 32-bit vs. 64-bit compatibility.
69 __u32 clear_sequence; /* seq. num. of clear event */
71 struct pps_ktime clear_tu; /* time of clear event */
77 __u32 clear_sequence; /* seq. num. of clear event */
79 struct pps_ktime_compat clear_tu; /* time of clear event */
87 struct pps_ktime clear_off_tu; /* offset compensation for clear */
[all …]
/linux/arch/powerpc/mm/book3s32/
H A Dhash_low.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 * Low-level exception handlers and MMU support
12 * This file contains low-level assembler routines for managing
25 #include <asm/asm-offsets.h>
26 #include <asm/feature-fixups.h>
27 #include <asm/code-patching-asm.h>
40 * - For ISI: _PAGE_PRESENT | _PAGE_EXEC
41 * - For DSI: _PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE if a write.
42 * r9 contains the SRR1 value, from which we use the MSR_PR bit.
[all …]
/linux/arch/m68k/fpsp040/
H A Dround.S21 | round --- round result according to precision/mode
36 | a0 is preserved and the g-r-s bits in d0 are cleared.
37 | The result is not typed - the tag field is invalid. The
40 | The INEX bit of USER_FPSR will be set if the rounded result was
41 | inexact (i.e. if any of the g-r-s bits were set).
51 | ;the appropriate g-r-s bits.
112 | If (g=1), then add 1 to l and if (r=s=0), then clear l
117 asll #1,%d0 |shift g-bit to c-bit
124 | ext_grs --- extract guard, round and sticky bits
144 moveml %d2/%d3,-(%a7) |make some temp registers
[all …]
/linux/drivers/w1/masters/
H A Damd_axi_w1.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * amd_axi_w1 - AMD 1Wire programmable logic bus host driver
5 * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
23 /* 1-wire AMD IP definition */
40 #define AXIW1_DONE BIT(0)
41 #define AXIW1_READY BIT(4)
42 #define AXIW1_PRESENCE BIT(31)
46 #define AXIW1_GO BIT(0)
48 #define AXI_RESET BIT(31)
49 #define AXIW1_READDATA BIT(0)
[all …]
/linux/drivers/net/wireless/ti/wl1251/
H A Dacx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (c) 1998-2007 Texas Instruments Incorporated
70 * bits 0 - 15: Reserved.
71 * bits 16 - 23: Version ID - The WiLink version ID
73 * bits 24 - 31: Chip ID - The WiLink chip ID.
93 /* 0 - Always active*/
94 /* 1 - Power down mode: light / fast sleep*/
95 /* 2 - ELP mode: Deep / Max sleep*/
188 * Bit Definition
191 * 13 Copy RX Status - when set, write three receive status words
[all …]
/linux/arch/powerpc/kernel/
H A Dcpu_setup_ppc970.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #include <asm/asm-offsets.h>
21 * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
26 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
27 rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */
33 rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ*) */
41 li r3,0x1200 /* enable i-fetch cacheability */
48 /* Clear HIOR */
51 mtspr SPRN_HIOR,0 /* Clear interrupt prefix */
77 li r11,5 /* clear DOZE and SLEEP */
[all …]
/linux/arch/sh/kernel/cpu/sh3/
H A Dserial-sh7720.c1 // SPDX-License-Identifier: GPL-2.0
14 if (port->mapbase == 0xa4430000) { /* SCIF0 */ in sh7720_sci_init_pins()
15 /* Clear PTCR bit 9-2; enable all scif pins but sck */ in sh7720_sci_init_pins()
18 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ in sh7720_sci_init_pins()
19 /* Clear PVCR bit 9-2 */ in sh7720_sci_init_pins()
24 if (port->mapbase == 0xa4430000) { /* SCIF0 */ in sh7720_sci_init_pins()
25 /* Clear PTCR bit 5-2; enable only tx and rx */ in sh7720_sci_init_pins()
28 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ in sh7720_sci_init_pins()
29 /* Clear PVCR bit 5-2 */ in sh7720_sci_init_pins()
/linux/drivers/usb/serial/
H A Dio_ti.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright (C) 1997-2002 Inside Out Networks, Inc.
6 * Feb-16-2001 DMI Added I2C structure definitions
7 * May-29-2002 gkh Ported to Linux
109 /* Set or Clear DTR (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
112 /* Set or Clear RTS (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
115 /* Set or Clear LOOPBACK (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
118 /* Set or Clear BREAK (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
125 /* Read-write group */
155 u8 bDataBits; /* 5..8 - data bits per character */
/linux/include/linux/mailbox/
H A Dmtk-cmdq-mailbox.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 #define CMDQ_INST_SIZE 8 /* instruction is 64-bit */
19 #define CMDQ_WFE_UPDATE BIT(31)
20 #define CMDQ_WFE_UPDATE_VALUE BIT(16)
21 #define CMDQ_WFE_WAIT BIT(15)
26 * bit 0-11: wait value
27 * bit 15: 1 - wait, 0 - no wait
28 * bit 16-27: update value
29 * bit 31: 1 - update, 0 - no update
47 * wait for event and clear
[all …]
/linux/drivers/comedi/drivers/
H A Dni_labpc_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * Register map (all registers are 8-bit)
13 #define STAT1_DAVAIL BIT(0)
14 #define STAT1_OVERRUN BIT(1)
15 #define STAT1_OVERFLOW BIT(2)
16 #define STAT1_CNTINT BIT(3)
17 #define STAT1_GATA0 BIT(5)
18 #define STAT1_EXTGATA0 BIT(6)
21 #define CMD1_TWOSCMP BIT(3)
23 #define CMD1_SCANEN BIT(7)
[all …]
H A Dni_daq_700.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Driver for DAQCard-700 DIO/AI
7 * COMEDI - Linux Control and Measurement Device Interface
13 * Description: National Instruments PCMCIA DAQCard-700
16 * Devices: [National Instruments] PCMCIA DAQ-Card-700 (ni_daq_700)
20 * The daqcard-700 appears in Comedi as a digital I/O subdevice (0) with
21 * 16 channels and a analog input subdevice (1) with 16 single-ended channels
24 * Digital: The channel 0 corresponds to the daqcard-700's output
25 * port, bit 0; channel 8 corresponds to the input port, bit 0.
27 * Digital direction configuration: channels 0-7 output, 8-15 input.
[all …]
/linux/arch/sparc/kernel/
H A Dspiterrs.S1 /* SPDX-License-Identifier: GPL-2.0 */
6 * We pass the AFAR in as-is, and we encode the status
7 * information as described in asm-sparc64/sfafsr.h
40 * error bits as-needed. We only clear them if the UE bit is
42 * if the CE bit is set.
44 * NOTE: UltraSparc-I/II have high and low UDB error
46 * present on those chips. UltraSparc-IIi only
74 1: /* Ok, now that we've latched the error state, clear the
105 .size __spitfire_access_error,.-__spitfire_access_error
112 * 1) single-bit ECC errors during UDB reads to system
[all …]
H A Dmisctrap.S1 /* SPDX-License-Identifier: GPL-2.0 */
9 .size arch_kgdb_breakpoint,.-arch_kgdb_breakpoint
15 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
23 .size __do_privact,.-__do_privact
37 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
50 .size do_mna,.-do_mna
57 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
68 .size do_lddfmna,.-do_lddfmna
75 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
87 .size do_stdfmna,.-do_stdfmna
[all …]
/linux/arch/arm/kernel/
H A Dphys2virt.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 1994-2002 Russell King
22 * __fixup_pv_table - patch the stub instructions with the delta between
36 subs r3, r8, #PAGE_OFFSET @ PHYS_OFFSET - PAGE_OFFSET
61 @ The Thumb-2 versions of the patchable sequences are
63 @ phys-to-virt: movw <reg>, #offset<31:21>
67 @ virt-to-phys (non-LPAE): movw <reg>, #offset<31:21>
71 @ virt-to-phys (LPAE): movw <reg>, #offset<31:21>
77 @ In the non-LPAE case, all patchable instructions are MOVW
79 @ second halfword of the opcode (the 16-bit immediate is encoded
[all …]
/linux/lib/
H A Dstmp_device.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2006-2007,2010 Freescale Semiconductor, Inc. All Rights Reserved.
22 * Clear the bit and poll it cleared. This is usually called with
23 * a reset address and mask being either SFTRST(bit 31) or CLKGATE
24 * (bit 30).
32 while ((readl(addr) & mask) && --timeout) in stmp_clear_poll_bit()
43 /* clear and poll SFTRST */ in stmp_reset_block()
48 /* clear CLKGATE */ in stmp_reset_block()
56 while ((!(readl(reset_addr) & STMP_MODULE_CLKGATE)) && --timeout) in stmp_reset_block()
61 /* clear and poll SFTRST */ in stmp_reset_block()
[all …]
/linux/drivers/edac/
H A Dr82600_edac.c14 * www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf
35 * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,
38 * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs
49 /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
102 * 2 NMI on Single Bit Eror (RW)
110 * write 1=Clear MBE status (must also
111 * clear SBE)
117 * write 1=Clear SBE status (must also
118 * clear MBE)
125 * 7:0 Address lines 30:24 - upper limit of
[all …]
/linux/include/linux/usb/
H A Dr8a66597.h1 // SPDX-License-Identifier: GPL-2.0
124 #define XTAL 0xC000 /* b15-14: Crystal selection */
133 #define HSE 0x0080 /* b7: Hi-speed enable */
135 #define DRPD 0x0020 /* b5: D+/- pull down control */
140 #define OVCBIT 0x8000 /* b15-14: Over-current bit */
141 #define OVCMON 0xC000 /* b15-14: Over-current monitor */
143 #define IDMON 0x0004 /* b3: ID-pin monitor */
144 #define LNST 0x0003 /* b1-0: D+, D- line status */
146 #define FS_KSTS 0x0002 /* Full-Speed K State */
147 #define FS_JSTS 0x0001 /* Full-Speed J State */
[all …]
/linux/drivers/i2c/busses/
H A Di2c-at91.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
18 #include <linux/dma-mapping.h>
30 #define AT91_TWI_START BIT(0) /* Send a Start Condition */
31 #define AT91_TWI_STOP BIT(1) /* Send a Stop Condition */
32 #define AT91_TWI_MSEN BIT(2) /* Master Transfer Enable */
33 #define AT91_TWI_MSDIS BIT(3) /* Master Transfer Disable */
34 #define AT91_TWI_SVEN BIT(4) /* Slave Transfer Enable */
35 #define AT91_TWI_SVDIS BIT(5) /* Slave Transfer Disable */
36 #define AT91_TWI_QUICK BIT(6) /* SMBus quick command */
[all …]
/linux/arch/mips/include/asm/
H A Ddma.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 * controller 1: channels 0-3, byte operations, ports 00-1F
33 * controller 2: channels 4-7, word operations, ports C0-DF
35 * - ALL registers are 8 bits only, regardless of transfer size
36 * - channel 4 is not used - cascades 1 into 2.
37 * - channels 0-3 are byte - addresses/counts are for physical bytes
38 * - channels 5-7 are word - addresses/counts are for physical words
39 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
40 * - transfer count loaded to registers is 1 less than actual count
41 * - controller 2 offsets are all even (2x offsets for controller 1)
[all …]
/linux/include/asm-generic/bitops/
H A Dinstrumented-atomic.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * This file provides wrappers with sanitizer instrumentation for atomic bit
8 * the below bit operations with an arch_ prefix (e.g. arch_set_bit(),
17 * set_bit - Atomically set a bit in memory
18 * @nr: the bit to set
24 * restricted to acting on a single-word quantity.
33 * clear_bit - Clears a bit in memory
34 * @nr: Bit to clear
46 * change_bit - Toggle a bit in memory
47 * @nr: Bit to change
[all …]
/linux/arch/x86/include/asm/
H A Dsync_bitops.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * These have to be done with inline assembly: that way the bit-setting
11 * is guaranteed to be atomic. All bit operations return 0 if the bit
14 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
22 * sync_set_bit - Atomically set a bit in memory
23 * @nr: the bit to set
30 * restricted to acting on a single-word quantity.
41 * sync_clear_bit - Clears a bit in memory
42 * @nr: Bit to clear
59 * sync_change_bit - Toggle a bit in memory
[all …]
/linux/arch/alpha/include/asm/
H A Ddma.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * include/asm-alpha/dma.h
6 * use ISA-compatible dma. The only extension is support for high-page
7 * registers that allow to set the top 8 bits of a 32-bit DMA address.
31 * controller 1: channels 0-3, byte operations, ports 00-1F
32 * controller 2: channels 4-7, word operations, ports C0-DF
34 * - ALL registers are 8 bits only, regardless of transfer size
35 * - channel 4 is not used - cascades 1 into 2.
36 * - channels 0-3 are byte - addresses/counts are for physical bytes
37 * - channels 5-7 are word - addresses/counts are for physical words
[all …]

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