Lines Matching +full:clear +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * include/asm-alpha/dma.h
6 * use ISA-compatible dma. The only extension is support for high-page
7 * registers that allow to set the top 8 bits of a 32-bit DMA address.
31 * controller 1: channels 0-3, byte operations, ports 00-1F
32 * controller 2: channels 4-7, word operations, ports C0-DF
34 * - ALL registers are 8 bits only, regardless of transfer size
35 * - channel 4 is not used - cascades 1 into 2.
36 * - channels 0-3 are byte - addresses/counts are for physical bytes
37 * - channels 5-7 are word - addresses/counts are for physical words
38 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
39 * - transfer count loaded to registers is 1 less than actual count
40 * - controller 2 offsets are all even (2x offsets for controller 1)
41 * - page registers for 5-7 don't use data bit 0, represent 128K pages
42 * - page registers for 0-3 use bit 0, represent 64K pages
48 * Address mapping for channels 0-3:
57 * Address mapping for channels 5-7:
66 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
67 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
68 * the hardware level, so odd-byte transfers aren't possible).
71 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
72 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
81 These may be due to SIO (PCI<->ISA bridge) chipset limitation, or
97 Maximum address for all the others is the complete 32-bit bus
117 Otherwise (Nautilus, RX164), we have to have 0-16 Mb DMA zone
123 #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
124 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
130 #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
132 #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
134 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
135 #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
136 #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
142 #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
144 #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
146 #define DMA2_RESET_REG 0xDA /* Master Clear (w) */
147 #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
148 #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
188 #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
223 /* Clear the 'DMA Pointer Flip Flop'.
226 * After that, keep track of it. :-)
227 * --- In order to do that, the DMA routines below should ---
228 * --- only be used while interrupts are disabled! ---
296 * Assumes dma flipflop is clear.
307 set_dma_page(dmanr, a>>16); /* set hipage last to enable 32-bit mode */ in set_dma_addr()
316 * Assumes dma flip-flop is clear.
317 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
321 count--; in set_dma_count()
338 * Assumes DMA flip-flop is clear.
345 /* using short to get 16-bit wrap around */ in get_dma_residue()