Lines Matching +full:clear +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-only
3 * amd_axi_w1 - AMD 1Wire programmable logic bus host driver
5 * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
23 /* 1-wire AMD IP definition */
40 #define AXIW1_DONE BIT(0)
41 #define AXIW1_READY BIT(4)
42 #define AXIW1_PRESENCE BIT(31)
46 #define AXIW1_GO BIT(0)
48 #define AXI_RESET BIT(31)
49 #define AXIW1_READDATA BIT(0)
51 #define AXIW1_READY_IRQ_EN BIT(4)
52 #define AXIW1_DONE_IRQ_EN BIT(0)
68 * amd_axi_w1_wait_irq_interruptible_timeout() - Wait for IRQ with timeout.
73 * Return: %0 - OK, %-EINTR - Interrupted, %-EBUSY - Timed out
81 iowrite32(IRQ, amd_axi_w1_local->base_addr + AXIW1_IRQE_REG); in amd_axi_w1_wait_irq_interruptible_timeout()
82 ret = wait_event_interruptible_timeout(amd_axi_w1_local->wait_queue, in amd_axi_w1_wait_irq_interruptible_timeout()
83 atomic_read(&amd_axi_w1_local->flag) != 0, in amd_axi_w1_wait_irq_interruptible_timeout()
86 dev_err(amd_axi_w1_local->dev, "Wait IRQ Interrupted\n"); in amd_axi_w1_wait_irq_interruptible_timeout()
87 return -EINTR; in amd_axi_w1_wait_irq_interruptible_timeout()
91 dev_err(amd_axi_w1_local->dev, "Wait IRQ Timeout\n"); in amd_axi_w1_wait_irq_interruptible_timeout()
92 return -EBUSY; in amd_axi_w1_wait_irq_interruptible_timeout()
95 atomic_set(&amd_axi_w1_local->flag, 0); in amd_axi_w1_wait_irq_interruptible_timeout()
100 * amd_axi_w1_touch_bit() - Performs the touch-bit function - write a 0 or 1 and reads the level.
103 * @bit: The level to write
107 static u8 amd_axi_w1_touch_bit(void *data, u8 bit) in amd_axi_w1_touch_bit() argument
113 /* Wait for READY signal to be 1 to ensure 1-wire IP is ready */ in amd_axi_w1_touch_bit()
114 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_READY) == 0) { in amd_axi_w1_touch_bit()
121 if (bit) in amd_axi_w1_touch_bit()
122 /* Read. Write read Bit command in register 0 */ in amd_axi_w1_touch_bit()
123 iowrite32(AXIW1_READBIT, amd_axi_w1_local->base_addr + AXIW1_INST_REG); in amd_axi_w1_touch_bit()
125 /* Write. Write tx Bit command in instruction register with bit to transmit */ in amd_axi_w1_touch_bit()
126 iowrite32(AXIW1_WRITEBIT + (bit & 0x01), in amd_axi_w1_touch_bit()
127 amd_axi_w1_local->base_addr + AXIW1_INST_REG); in amd_axi_w1_touch_bit()
129 /* Write Go signal and clear control reset signal in control register */ in amd_axi_w1_touch_bit()
130 iowrite32(AXIW1_GO, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_touch_bit()
133 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_DONE) != 1) { in amd_axi_w1_touch_bit()
140 if (bit) in amd_axi_w1_touch_bit()
141 val = (u8)(ioread32(amd_axi_w1_local->base_addr + AXIW1_DATA_REG) & AXIW1_READDATA); in amd_axi_w1_touch_bit()
143 /* Clear Go signal in register 1 */ in amd_axi_w1_touch_bit()
144 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_touch_bit()
150 * amd_axi_w1_read_byte - Performs the read byte function.
161 /* Wait for READY signal to be 1 to ensure 1-wire IP is ready */ in amd_axi_w1_read_byte()
162 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_READY) == 0) { in amd_axi_w1_read_byte()
170 iowrite32(AXIW1_READBYTE, amd_axi_w1_local->base_addr + AXIW1_INST_REG); in amd_axi_w1_read_byte()
172 /* Write Go signal and clear control reset signal in control register */ in amd_axi_w1_read_byte()
173 iowrite32(AXIW1_GO, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_read_byte()
176 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_DONE) != 1) { in amd_axi_w1_read_byte()
182 /* Retrieve LSB bit in data register to get RX byte */ in amd_axi_w1_read_byte()
183 val = (u8)(ioread32(amd_axi_w1_local->base_addr + AXIW1_DATA_REG) & 0x000000FF); in amd_axi_w1_read_byte()
185 /* Clear Go signal in control register */ in amd_axi_w1_read_byte()
186 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_read_byte()
192 * amd_axi_w1_write_byte - Performs the write byte function.
202 /* Wait for READY signal to be 1 to ensure 1-wire IP is ready */ in amd_axi_w1_write_byte()
203 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_READY) == 0) { in amd_axi_w1_write_byte()
210 /* Write tx Byte command in instruction register with bit to transmit */ in amd_axi_w1_write_byte()
211 iowrite32(AXIW1_WRITEBYTE + val, amd_axi_w1_local->base_addr + AXIW1_INST_REG); in amd_axi_w1_write_byte()
213 /* Write Go signal and clear control reset signal in register 1 */ in amd_axi_w1_write_byte()
214 iowrite32(AXIW1_GO, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_write_byte()
217 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_DONE) != 1) { in amd_axi_w1_write_byte()
224 /* Clear Go signal in control register */ in amd_axi_w1_write_byte()
225 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_write_byte()
229 * amd_axi_w1_reset_bus() - Issues a reset bus sequence.
240 /* Reset 1-wire Axi IP */ in amd_axi_w1_reset_bus()
241 iowrite32(AXI_RESET, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_reset_bus()
243 /* Wait for READY signal to be 1 to ensure 1-wire IP is ready */ in amd_axi_w1_reset_bus()
244 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_READY) == 0) { in amd_axi_w1_reset_bus()
251 iowrite32(AXIW1_INITPRES, amd_axi_w1_local->base_addr + AXIW1_INST_REG); in amd_axi_w1_reset_bus()
253 /* Write Go signal and clear control reset signal in register 1 */ in amd_axi_w1_reset_bus()
254 iowrite32(AXIW1_GO, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_reset_bus()
257 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_DONE) != 1) { in amd_axi_w1_reset_bus()
262 /* Retrieve MSB bit in status register to get failure bit */ in amd_axi_w1_reset_bus()
263 if ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_PRESENCE) != 0) in amd_axi_w1_reset_bus()
266 /* Clear Go signal in control register */ in amd_axi_w1_reset_bus()
267 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_reset_bus()
272 /* Reset the 1-wire AXI IP. Put the IP in reset state and clear registers */
275 iowrite32(AXI_RESET, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_reset()
276 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_INST_REG); in amd_axi_w1_reset()
277 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_IRQE_REG); in amd_axi_w1_reset()
278 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_STAT_REG); in amd_axi_w1_reset()
279 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_DATA_REG); in amd_axi_w1_reset()
287 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_IRQE_REG); in amd_axi_w1_irq()
289 atomic_set(&amd_axi_w1_local->flag, 1); in amd_axi_w1_irq()
290 wake_up_interruptible(&amd_axi_w1_local->wait_queue); in amd_axi_w1_irq()
297 struct device *dev = &pdev->dev; in amd_axi_w1_probe()
305 return -ENOMEM; in amd_axi_w1_probe()
307 lp->dev = dev; in amd_axi_w1_probe()
308 lp->base_addr = devm_platform_ioremap_resource(pdev, 0); in amd_axi_w1_probe()
309 if (IS_ERR(lp->base_addr)) in amd_axi_w1_probe()
310 return PTR_ERR(lp->base_addr); in amd_axi_w1_probe()
312 lp->irq = platform_get_irq(pdev, 0); in amd_axi_w1_probe()
313 if (lp->irq < 0) in amd_axi_w1_probe()
314 return lp->irq; in amd_axi_w1_probe()
316 rc = devm_request_irq(dev, lp->irq, &amd_axi_w1_irq, IRQF_TRIGGER_HIGH, DRIVER_NAME, lp); in amd_axi_w1_probe()
321 init_waitqueue_head(&lp->wait_queue); in amd_axi_w1_probe()
328 if (ioread32(lp->base_addr + AXIW1_IPID_REG) != AXIW1_IPID) { in amd_axi_w1_probe()
329 dev_err(dev, "AMD 1-wire IP not detected in hardware\n"); in amd_axi_w1_probe()
330 return -ENODEV; in amd_axi_w1_probe()
343 val = ioread32(lp->base_addr + AXIW1_IPVER_REG); in amd_axi_w1_probe()
350 return -ENODEV; in amd_axi_w1_probe()
353 lp->bus_host.data = lp; in amd_axi_w1_probe()
354 lp->bus_host.touch_bit = amd_axi_w1_touch_bit; in amd_axi_w1_probe()
355 lp->bus_host.read_byte = amd_axi_w1_read_byte; in amd_axi_w1_probe()
356 lp->bus_host.write_byte = amd_axi_w1_write_byte; in amd_axi_w1_probe()
357 lp->bus_host.reset_bus = amd_axi_w1_reset_bus; in amd_axi_w1_probe()
362 rc = w1_add_master_device(&lp->bus_host); in amd_axi_w1_probe()
375 w1_remove_master_device(&lp->bus_host); in amd_axi_w1_remove()
379 { .compatible = "amd,axi-1wire-host" },