Lines Matching +full:clear +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 * Low-level exception handlers and MMU support
12 * This file contains low-level assembler routines for managing
25 #include <asm/asm-offsets.h>
26 #include <asm/feature-fixups.h>
27 #include <asm/code-patching-asm.h>
40 * - For ISI: _PAGE_PRESENT | _PAGE_EXEC
41 * - For DSI: _PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE if a write.
42 * r9 contains the SRR1 value, from which we use the MSR_PR bit.
48 * Uses r0, r3 - r6, r8, r10, ctr, lr.
53 lis r8, (mmu_hash_lock - PAGE_OFFSET)@h
54 ori r8, r8, (mmu_hash_lock - PAGE_OFFSET)@l
62 bne- 11b
64 bne- 10b
67 /* Get PTE (linux-style) and check access */
71 lwz r5,PGDIR(r8) /* virt page-table root */
77 bne- .Lhash_page_out /* return if usermode */
79 bnelr-
92 beq- .Lhash_page_out /* return if no mapping */
96 8 or 0xc) and we have had a not-taken conditional branch
98 beqlr-
112 * Update the linux PTE atomically. We do the lwarx up-front
115 * to update the PTE to set _PAGE_HASHPTE. -- paulus.
118 lwarx r6,0,r8 /* get linux-style pte, flag word */
124 andc r5,r6,r5 /* Clear _PAGE_WRITE when Ks = 1 && MSR[PR] = 0 */
129 rlwinm r0,r3,32-3,24,24 /* _PAGE_WRITE access -> _PAGE_DIRTY */
132 bne- .Lhash_page_out /* return if access not permitted */
134 bnelr-
143 lwz r10,-PTE_FLAGS_OFFSET(r8)
147 bne- .Lretry /* retry if someone got there first */
154 lis r8, (mmu_hash_lock - PAGE_OFFSET)@ha
156 stw r0, (mmu_hash_lock - PAGE_OFFSET)@l(r8)
163 lis r8, (mmu_hash_lock - PAGE_OFFSET)@ha
165 stw r0, (mmu_hash_lock - PAGE_OFFSET)@l(r8)
176 * the accessed bit) have already been done and that there is actually
191 * _PAGE_HASHPTE bit to be a reliable indication of whether
195 * covered by a BAT). -- paulus
198 rlwinm r0,r9,0,17,15 /* clear bit 16 (MSR_EE) */
199 rlwinm r0,r0,0,28,26 /* clear MSR_DR */
204 lis r6, (mmu_hash_lock - PAGE_OFFSET)@ha
205 addi r6, r6, (mmu_hash_lock - PAGE_OFFSET)@l
208 bne- 11f
239 lwz r10,-PTE_FLAGS_OFFSET(r8)
244 bne- 1b
256 lis r6, (mmu_hash_lock - PAGE_OFFSET)@ha
257 addi r6, r6, (mmu_hash_lock - PAGE_OFFSET)@l
260 stw r0,0(r6) /* clear mmu_hash_lock */
281 * bit in the linux PTE in memory. The value passed in r6 should
284 * This procedure modifies r0, r3 - r6, r8, cr0.
285 * -- paulus.
293 Hash_msk = (((1 << Hash_bits) - 1) * 64)
295 /* defines for the PTE format for 32-bit PPCs */
309 #define HASH_LEFT 31-(LG_PTEG_SIZE+Hash_bits-1)
310 #define HASH_RIGHT 31-LG_PTEG_SIZE
314 /* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */
316 rlwinm r5,r5,0,~3 /* Clear PP bits */
318 rlwinm r8,r5,32-9,30,30 /* _PAGE_WRITE -> PP msb */
319 rlwinm r0,r5,32-6,30,30 /* _PAGE_DIRTY -> PP msb */
321 bge- 1f /* Kernelspace ? Skip */
323 1: ori r8,r8,0xe04 /* clear out reserved bits */
326 rlwinm r8,r8,0,~_PAGE_COHERENT /* clear M (coherence not required) */
334 /* Construct the high word of the PPC-style PTE (r5) */
337 SET_V(r5) /* set V (valid) bit */
343 0: lis r0, (Hash_base - PAGE_OFFSET)@h /* base address of hash table */
344 1: rlwimi r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
345 2: rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
350 * Test the _PAGE_HASHPTE bit in the old linux PTE, and skip the search
351 * if it is clear, meaning that the HPTE isn't there already...
359 addi r4,r3,-HPTE_SIZE
367 ori r5,r5,PTE_H /* set H (secondary hash) bit */
369 xori r4,r4,(-PTEG_SIZE & 0xffff)
370 addi r4,r4,-HPTE_SIZE
376 xori r5,r5,PTE_H /* clear H bit again */
380 addi r4,r3,-HPTE_SIZE /* search primary PTEG */
382 TST_V(r6) /* test valid bit */
388 ori r5,r5,PTE_H /* set H (secondary hash) bit */
390 xori r4,r4,(-PTEG_SIZE & 0xffff)
391 addi r4,r4,-HPTE_SIZE
397 xori r5,r5,PTE_H /* clear H bit again */
409 lis r4, (next_slot - PAGE_OFFSET)@ha /* get next evict slot */
410 lwz r6, (next_slot - PAGE_OFFSET)@l(r4)
435 * address. :-) The tlbie above is mainly to make sure that this CPU comes
439 * state with the V bit set.
443 CLR_V(r5,r0) /* clear V (valid) bit in PTE */
450 STPTE r5,0(r4) /* finally set V bit in PTE */
476 * the _PAGE_HASHPTE bit to be a reliable indication of
480 * covered by a BAT). -- paulus
483 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
484 rlwinm r0,r0,0,28,26 /* clear MSR_DR */
502 addi r6,r6,-1
511 /* Construct the high word of the PPC-style PTE (r11) */
514 SET_V(r11) /* set V (valid) bit */
517 lis r9, (mmu_hash_lock - PAGE_OFFSET)@ha
518 addi r9, r9, (mmu_hash_lock - PAGE_OFFSET)@l
524 bne- 11f
535 * Check the _PAGE_HASHPTE bit in the linux PTE. If it is
536 * already clear, we're done (for this pte). If not,
537 * clear it (atomically) and proceed. -- paulus.
541 beq 8f /* done if HASHPTE is already clear */
542 rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */
544 bne- 33b
550 0: lis r8, (Hash_base - PAGE_OFFSET)@h /* base address of hash table */
551 1: rlwimi r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
552 2: rlwinm r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
558 addi r12,r8,-HPTE_SIZE
566 ori r11,r11,PTE_H /* set H (secondary hash) bit */
569 xori r12,r12,(-PTEG_SIZE & 0xffff)
570 addi r12,r12,-HPTE_SIZE
575 xori r11,r11,PTE_H /* clear H again */
576 bne- 4f /* should rarely fail to find it */
585 81: addi r6,r6,-1
598 stw r0,0(r9) /* clear mmu_hash_lock */