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/linux/drivers/media/platform/nxp/imx8-isi/
H A Dimx8-isi-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2019-2020 NXP
12 /* Channel Control Register */
33 /* Channel Image Control Register */
98 #define CHNL_IMG_CTRL_DEC_X_MASK GENMASK(11, 10)
113 /* Channel Output Buffer Control Register */
136 /* Channel Image Configuration */
143 /* Channel Interrupt Enable Register */
153 /* Channel Status Register */
179 /* Channel Scale Factor Register */
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dbrcmu_d11.h1 // SPDX-License-Identifier: ISC
13 /* A chanspec (channel specification) holds the channel number, band,
20 /* bit 0~7 channel number
21 * for 80+80 channels: bit 0~3 low channel id, bit 4~7 high channel id
30 /* bit 8~16 for dot 11n IO types
32 * bit 10~11 bandwidth
51 /* bit 8~16 for dot 11ac IO types
53 * bit 11~13 bandwidth
73 #define BRCMU_CHSPEC_D11AC_BW_SHIFT 11
100 BRCMU_CHAN_SB_NONE = -1,
[all …]
/linux/drivers/net/wireless/marvell/mwifiex/
H A D11h.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2011-2020 NXP
14 priv->state_11h.is_11h_enabled = true; in mwifiex_init_11h_params()
15 priv->state_11h.is_11h_active = false; in mwifiex_init_11h_params()
20 return priv->state_11h.is_11h_active; in mwifiex_is_11h_active()
22 /* This function appends 11h info to a buffer while joining an
39 radio_type = mwifiex_band_to_radio_type((u8) bss_desc->bss_band); in mwifiex_11h_process_infra_join()
40 sband = priv->wdev.wiphy->bands[radio_type]; in mwifiex_11h_process_infra_join()
43 cap->header.type = cpu_to_le16(WLAN_EID_PWR_CAPABILITY); in mwifiex_11h_process_infra_join()
44 cap->header.len = cpu_to_le16(2); in mwifiex_11h_process_infra_join()
[all …]
/linux/drivers/net/wireless/zydas/zd1211rw/
H A Dzd_rf_uw2453.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ZD1211 USB-WLAN driver for Linux
4 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
5 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
20 /* The 3-wire serial interface provides access to 8 write-only registers.
24 /* For channel tuning, we have to configure registers 1 (synthesizer), 2 (synth
29 * of different VCO configurations on channel 1 until we detect a PLL lock.
35 * autocal configuration, which has a fixed (as opposed to per-channel) VCO
39 /* The per-channel synth values for all standard VCO configurations. These get
52 RF_CHANNEL(11) = 0x77,
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_lp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 IEEE 802.11a/g LP-PHY driver
7 Copyright (c) 2008-2009 Michael Buesch <m@bues.ch>
23 static inline u16 channel2freq_lp(u8 channel) in channel2freq_lp() argument
25 if (channel < 14) in channel2freq_lp()
26 return (2407 + 5 * channel); in channel2freq_lp()
27 else if (channel == 14) in channel2freq_lp()
29 else if (channel < 184) in channel2freq_lp()
30 return (5000 + 5 * channel); in channel2freq_lp()
32 return (4000 + 5 * channel); in channel2freq_lp()
[all …]
/linux/drivers/clk/bcm/
H A Dclk-sr.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-sr.h>
12 #include "clk-iproc.h"
38 .reset = RESET_VAL(0x0, 12, 11),
49 .channel = BCM_SR_GENPLL0_125M_CLK,
55 .channel = BCM_SR_GENPLL0_SCR_CLK,
61 .channel = BCM_SR_GENPLL0_250M_CLK,
67 .channel = BCM_SR_GENPLL0_PCIE_AXI_CLK,
73 .channel = BCM_SR_GENPLL0_PAXC_AXI_X2_CLK,
[all …]
H A Dclk-cygnus.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/bcm-cygnus.h>
14 #include "clk-iproc.h"
45 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
51 .reset = RESET_VAL(0x0, 11, 10),
63 .channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
69 .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
75 .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
81 .channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK,
[all …]
H A Dclk-nsp.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-nsp.h>
12 #include "clk-iproc.h"
33 CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init);
38 .reset = RESET_VAL(0x0, 11, 10),
48 .channel = BCM_NSP_GENPLL_PHY_CLK,
54 .channel = BCM_NSP_GENPLL_ENET_SW_CLK,
60 .channel = BCM_NSP_GENPLL_USB_PHY_REF_CLK,
66 .channel = BCM_NSP_GENPLL_IPROCFAST_CLK,
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Drf.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2010 Realtek Corporation.*/
17 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 3); in rtl8821ae_phy_rf6052_set_bandwidth()
18 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 3); in rtl8821ae_phy_rf6052_set_bandwidth()
21 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 1); in rtl8821ae_phy_rf6052_set_bandwidth()
22 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 1); in rtl8821ae_phy_rf6052_set_bandwidth()
25 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 0); in rtl8821ae_phy_rf6052_set_bandwidth()
26 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 0); in rtl8821ae_phy_rf6052_set_bandwidth()
38 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl8821ae_phy_rf6052_set_cck_txpower()
48 if (rtlefuse->eeprom_regulatory != 0) in rtl8821ae_phy_rf6052_set_cck_txpower()
[all …]
/linux/drivers/gpu/drm/mcde/
H A Dmcde_display_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 /* Channel interrupts */
74 #define MCDE_EXTSRCXCONF_BPP_YCBCR422 11
134 #define MCDE_OVLXCR_BURSTSIZE_HW_8W 11
153 #define MCDE_OVLXCR_ROTBURSTSIZE_HW_8W 11
164 #define MCDE_OVLXCONF_EXTSRC_ID_SHIFT 11
211 #define MCDE_OVLXCOMP_CH_ID_SHIFT 11
218 /* DPI/TV configuration registers, channel A and B */
232 /* TV blanking control register 1, channel A and B */
235 #define MCDE_TVBL1_BEL1_SHIFT 0 /* VFP vertical front porch 11 bits */
[all …]
/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Dscan.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
13 * enum iwl_scan_subcmd_ids - scan commands
33 * struct iwl_ssid_ie - directed scan network information element
37 * each channel may select different ssids from among the 20 entries.
53 #define IWL_SCAN_MAX_PROFILES 11
78 * struct iwl_scan_offload_blocklist - SCAN_OFFLOAD_BLACKLIST_S
81 * @client_bitmap: clients ignore this entry - enum scan_framework_client
[all …]
H A Dnvm-reg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
11 * enum iwl_regulatory_and_nvm_subcmd_ids - regulatory/NVM commands
61 * enum iwl_nvm_access_op - NVM access opcode
71 * enum iwl_nvm_access_target - target of the NVM_ACCESS_CMD
83 * enum iwl_nvm_section_type - section types for NVM_ACCESS_CMD
99 NVM_SECTION_TYPE_MAC_OVERRIDE = 11,
105 * struct iwl_nvm_access_cmd - Request the device to send an NVM section
[all …]
/linux/drivers/comedi/drivers/
H A Dplx9080.h1 /* SPDX-License-Identifier: GPL-2.0+ */
26 * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
32 * Describes the format of a scatter-gather DMA descriptor for the PLX
33 * PCI 9080. All members are raw, little-endian register values that
35 * corresponding registers for the DMA channel.
37 * The DMA descriptors must be aligned on a 16-byte boundary. Bits 3:0
99 /* DMA Channel Priority */
101 #define PLX_MARBR_PRIO_DMA0 (BIT(19) * 1) /* DMA channel 0 has priority */
102 #define PLX_MARBR_PRIO_DMA1 (BIT(19) * 2) /* DMA channel 1 has priority */
137 /* Big Endian Byte Lane Mode - use most significant byte lanes */
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822b.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
26 ether_addr_copy(efuse->addr, map->e.mac_addr); in rtw8822be_efuse_parsing()
32 ether_addr_copy(efuse->addr, map->u.mac_addr); in rtw8822bu_efuse_parsing()
38 ether_addr_copy(efuse->addr, map->s.mac_addr); in rtw8822bs_efuse_parsing()
43 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8822b_read_efuse()
49 efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(7)); in rtw8822b_read_efuse()
50 efuse->rfe_option = map->rfe_option; in rtw8822b_read_efuse()
51 efuse->rf_board_option = map->rf_board_option; in rtw8822b_read_efuse()
52 efuse->crystal_cap = map->xtal_k; in rtw8822b_read_efuse()
[all …]
/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-facebook-minipack.dts1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "ast2500-facebook-netbmc-common.dtsi"
9 compatible = "facebook,minipack-bmc", "aspeed,ast2500";
23 * i2c switch 2-0070, pca9548, 8 child channels assigned
24 * with bus number 16-23.
36 * i2c switch 8-0070, pca9548, 8 child channels assigned
37 * with bus number 24-31.
49 * i2c switch 9-0070, pca9548, 8 child channels assigned
50 * with bus number 32-39.
[all …]
/linux/arch/powerpc/boot/dts/
H A Dasp834x-redboot.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
12 compatible = "analogue-and-micro,asp8347e";
13 #address-cells = <1>;
14 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <32768>;
[all …]
/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-nvm-parse.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2005-2014, 2018-2023 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
14 #include "iwl-drv.h"
15 #include "iwl-modparams.h"
16 #include "iwl-nvm-parse.h"
17 #include "iwl-prph.h"
18 #include "iwl-io.h"
19 #include "iwl-csr.h"
[all …]
/linux/drivers/hwmon/
H A Dlenovo-ec-sensors.c1 // SPDX-License-Identifier: GPL-2.0+
9 * - CPU temperature
10 * - DIMM temperature
11 * - Chassis zone temperatures
12 * - CPU fan RPM
13 * - DIMM fan RPM
14 * - Chassis fans RPM
69 static int px_temp_map[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
89 static int gen_temp_map[] = {0, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
106 static int px_fan_map[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9002_phy.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
20 * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
27 * into a single-chip and require less programming.
29 * The following single-chips exist with a respective embedded radio:
31 * AR9280 - 11n dual-band 2x2 MIMO for PCIe
32 * AR9281 - 11n single-band 1x2 MIMO for PCIe
33 * AR9285 - 11n single-band 1x1 for PCIe
34 * AR9287 - 11n single-band 2x2 MIMO for PCIe
36 * AR9220 - 11n dual-band 2x2 MIMO for PCI
37 * AR9223 - 11n single-band 2x2 MIMO for PCI
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
19 The first cell is the unique device channel number as indicated by this
32 10: Multi-Channel Display Engine MCDE RX
33 11: UART port 2
[all …]
/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
34 * 11 Reserved
52 * [15:0] Two bit for each channel (channel 0 ~ 7). Each two bits are the buffer
53 * pointer for the last encoded frame of the corresponding channel.
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
[all …]
/linux/drivers/media/radio/si470x/
H A Dradio-si470x.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * drivers/media/radio/si470x/radio-si470x.h
12 #define DRIVER_NAME "radio-si470x"
24 #include <media/v4l2-common.h>
25 #include <media/v4l2-ioctl.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-event.h>
28 #include <media/v4l2-device.h>
42 #define DEVICEID_MFGID 0x0fff /* bits 11..00: Manufacturer ID */
53 #define POWERCFG_RDSM 0x0800 /* bits 11..11: RDS Mode (Si4701 only) */
[all …]
/linux/drivers/staging/rtl8723bs/include/
H A Dieee80211.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
33 RTL871X_HOSTAPD_SET_ASSOC_AP_ADDR = 11,
60 #define WLAN_STA_HT BIT(11)
141 /* Sub-Element */
261 #define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */
343 #define IEEE80211_OFDM_RATE_54MB_MASK (1<<11)
438 ,-------------------------------------------------------------------.
440 |------|------|---------|---------|---------|------|---------|------|
443 `-------------------------------------------------------------------'
[all …]
/linux/drivers/net/ethernet/microchip/
H A Dlan743x_main.h1 /* SPDX-License-Identifier: GPL-2.0+ */
152 #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) argument
153 #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) argument
154 #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) argument
157 #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) argument
158 #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) argument
159 #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) argument
174 #define MAC_CR_ASD_ BIT(11)
208 #define MAC_MII_ACC_PHY_ADDR_SHIFT_ (11)
233 #define MAC_WUCSR_EEE_RX_WAKE_ BIT(11)
[all …]
/linux/sound/usb/caiaq/
H A Dcontrol.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 struct snd_usb_caiaqdev *cdev = caiaqdev(chip->card); in control_info()
25 int pos = kcontrol->private_value; in control_info()
29 uinfo->count = 1; in control_info()
32 switch (cdev->chip.usb_id) { in control_info()
37 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; in control_info()
38 uinfo->value.integer.min = 0; in control_info()
39 uinfo->value.integer.max = 2; in control_info()
54 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; in control_info()
55 uinfo->value.integer.min = 0; in control_info()
[all …]

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