Lines Matching +full:channel +full:- +full:11

1 /* SPDX-License-Identifier: GPL-2.0 */
26 /* Channel interrupts */
74 #define MCDE_EXTSRCXCONF_BPP_YCBCR422 11
134 #define MCDE_OVLXCR_BURSTSIZE_HW_8W 11
153 #define MCDE_OVLXCR_ROTBURSTSIZE_HW_8W 11
164 #define MCDE_OVLXCONF_EXTSRC_ID_SHIFT 11
211 #define MCDE_OVLXCOMP_CH_ID_SHIFT 11
218 /* DPI/TV configuration registers, channel A and B */
232 /* TV blanking control register 1, channel A and B */
235 #define MCDE_TVBL1_BEL1_SHIFT 0 /* VFP vertical front porch 11 bits */
236 #define MCDE_TVBL1_BSL1_SHIFT 16 /* VSW vertical sync pulse width 11 bits */
238 /* Pixel processing TV start line, channel A and B */
241 #define MCDE_TVISL_FSL1_SHIFT 0 /* Field 1 identification start line 11 bits */
242 #define MCDE_TVISL_FSL2_SHIFT 16 /* Field 2 identification start line 11 bits */
252  * HBP horizontal back porch 11 bits horizontal offset
253  * 0 = 1 pixel HBP, 255 = 256 pixels, so actual value - 1
262 #define MCDE_TVLBALW_LBW_SHIFT 0 /* HSW horizonal sync width, line blanking width 11 bits */
263 #define MCDE_TVLBALW_ALW_SHIFT 16 /* HFP horizontal front porch, active line width 11 bits */
265 /* TV blanking control register 1, channel A and B */
268 #define MCDE_TVBL2_BEL2_SHIFT 0 /* Field 2 blanking end line 11 bits */
269 #define MCDE_TVBL2_BSL2_SHIFT 16 /* Field 2 blanking start line 11 bits */
337 /* Channel config 0..3 */
348 /* Channel status 0..3 */
359 /* Sync settings for channel 0..3 */
376 /* Software sync triggers for channel 0..3 */
403 /* Pixel processing control registers for channel A B,  */
421 #define MCDE_CRX0_FLICKMODE_SHIFT 11
514 /* Channel A+B control registers */