1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  *  TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
34  * 11 Reserved
52  * [15:0] Two bit for each channel (channel 0 ~ 7). Each two bits are the buffer
53  * pointer for the last encoded frame of the corresponding channel.
76  * 0->3 4 VLC data buffer in DDR (1M each)
77  * 0->7 8 VLC data buffer in DDR (512k each)
120 /* [15:0] SEN_EN_CH[n] SENIF original frame capture enable for each channel */
125 /* The ID for channel selected for encoding operation */
147 /* DDR-DPR Burst Read Enable */
157  * 0 Single R/W Access (Host <-> DDR)
158  * 1 Burst R/W Access (Host <-> DPR)
162 /* The original frame capture pointer. Two bits for each channel */
174  * [15:0]: ENC_BUF_PTR_REC[31:16] Two bit for each channel (channel 8 ~ 15).
175  * Each two bits are the buffer pointer for the last encoded frame of a channel
179 /* Current MV Flag Status Pointer for Channel n. (Read only) */
190  * [15:0] Reset Current MV Flag Status Pointer for Channel n (one bit each)
196  * Inter_Mode Start. 2-nd bit? A guess. Missing in datasheet. Without this bit
203  * De-interlacer Mode
205  * 0 Normal Un-Shuffled Frame
210  * 11: Un-used
211  * 10: down-sample to 1/4
212  * 01: down-sample to 1/2
213  * 00: down-sample disabled
218  * 11: Un-used
219  * 10: down-sample to 1/4
220  * 01: down-sample to 1/2
221  * 00: down-sample disabled
289 /* OSD enable bit for each channel */
292 /* 0x0280 ~ 0x029c - Motion Vector for 1st 4x4 Block, e.g., 80 (X), 84 (Y) */
294 /* 0x02a0 ~ 0x02bc - Motion Vector for 2nd 4x4 Block, e.g., A0 (X), A4 (Y) */
296 /* 0x02c0 ~ 0x02dc - Motion Vector for 3rd 4x4 Block, e.g., C0 (X), C4 (Y) */
298 /* 0x02e0 ~ 0x02fc - Motion Vector for 4th 4x4 Block, e.g., E0 (X), E4 (Y) */
336 /* 0x0800 ~ 0x09ff - Quantization TABLE Values */
339 /* Valid channel value [0; f], frame value [0; 3] */
340 #define TW5864_RT_CNTR_CH_FRM(channel, frame) \  argument
341 	(0x0c00 | (channel << 4) | (frame << 2))
371 /* [15:0] Horizontal Mirror for channel n */
373 /* [15:0] Vertical Mirror for channel n */
406  * 1: the bus mapped Channel n Full D1
407  * 0: the bus mapped Channel n Half D1
412  * 0 The bus mapped Channel select partA Mode
413  * 1 The bus mapped Channel select partB Mode
422  * Swap byte order of VLC stream in d-word.
497 /* 0x2000 ~ 0x2ffc - H264 Stream Memory Map */
509 /* 0x4000 ~ 0x4ffc - Audio Register Map */
524 /* Record path PCM Audio enable bit for each channel */
545 /* Channel ID used to select audio channel (0 to 16) for loopback */
558 /* Record path ADPCM audio channel enable, one bit for each */
560 /* Speaker path ADPCM audio channel enable */
571  * Bit[11:9] ch3
598 /* [3:0] rd ch0, [7:4] rd ch1, [11:8] wr ch0, [15:12] wr ch1 */
605  * Bit[11:8] ch2
642  * or ADPCM(1) audio data sent to PC. One bit for each channel
699  * The system / DDR clock (166 MHz) is generated with an on-chip system clock
758  * 11 270 ~ 700 MHz
776  * 11 x1/8
829 /* 0x8800 ~ 0x88fc - Interrupt Register Map */
848  * 1 High level or pos-edge is assertion
849  * 0 Low level or neg-edge is assertion
873  * Bit[11]: gpio 7 interrupt
891  * Bit[11:15]: Reserved
912 /* 0x9000 ~ 0x920c - Video Capture (VIF) Register Map */
915  * 1 Channel Enabled
916  * 0 Channel Disabled
920  * [15:0] H264EN_CH_EN[n] H264 Encoding Path Enable for channel
921  * 1 Channel Enabled
922  * 0 Channel Disabled
927  * channel n
933  * H264EN_CH_PROG[n] H264 Encoding Path channel n is progressive
940  * H264 Encoding Path maximum number of channel on BUS n
965  * H264EN_CHn_FMT H264 Encoding Path Format configuration of Channel n
969  * 11 D1 with 1/2 size in X (for CIF frame)
984  * H264EN_RATE_CNTL_BUSm_CHn H264 Encoding Path BUS m Rate Control for Channel n
986 #define TW5864_H264EN_RATE_CNTL_LO_WORD(bus, channel) \  argument
987 	(0x9100 + bus * 0x20 + channel * 0x08)
988 #define TW5864_H264EN_RATE_CNTL_HI_WORD(bus, channel) \  argument
989 	(0x9104 + bus * 0x20 + channel * 0x08)
992  * H264EN_BUSm_MAP_CHn The 16-to-1 MUX configuration register for each encoding
993  * channel (total of 16 channels). Four bits for each channel.
1012 /* 0xa000 ~ 0xa8ff - DDR Controller Register Map */
1068  * 1 DDR self-test mode
1072  * 0 DDR self-test single read/write
1073  * 1 DDR self-test burst read/write
1077  * 0 DDR self-test write command
1078  * 1 DDR self-test read command
1090 /* [7:0] The maximum data of one burst in DDR self-test mode */
1092 /* [15:0] The maximum burst counter (bit 15~0) in DDR self-test mode */
1094 /* The maximum burst counter (bit 31~16) in DDR self-test mode */
1096 /* [0]: Start one DDR self-test */
1098 /* The maximum error counter (bit 15 ~ 0) in DDR self-test */
1103 /* The maximum error counter (bit 30 ~ 16) in DDR self-test */
1105 /* DDR self-test end flag */
1114 /* 0xb004 ~ 0xb018 - HW version/ARB12 Register Map */
1148 /* 0xb800 ~ 0xb80c - Indirect Access Register Map */
1180 /* 0xc000 ~ 0xc7fc - Preview Register Map */
1184  * 1 Channel Enabled
1185  * 0 Channel Disabled
1189  * [15:0] PCI Preview Path Enable for channel n
1190  * 1 Channel Enable
1191  * 0 Channel Disable
1195 /* 0xc800 ~ 0xc804 - JPEG Capture Register Map */
1197 /* 0xd000 ~ 0xd0fc - JPEG Control Register Map */
1200 /* 0xe000 ~ 0xfc04 - Motion Vector Register Map */
1234 /* 0x18000 ~ 0x181fc - PCI Master/Slave Control Map */
1271 /* audio master channel enable */
1312  * Every channel of preview and audio have ping-pong buffers in system memory,
1375  * PREV_PCI_ENB_CHN[0] Enable 9th preview channel (9CIF prev) or 1D1 channel in
1377  * PREV_PCI_ENB_CHN[1] Enable 10th preview channel
1407 /* 0x80000 ~ 0x87fff - DDR Burst RW Register Map */
1411 /* Length of 32-bit data burst */
1444 /* 0x84000 - 0x87ffc */
1453 /* Allowed channel values: [0; 3] */
1454 /* Read-only register */
1455 #define TW5864_INDIR_VIN_0(channel) (0x000 + channel * 0x010)  argument
1469  * 1 Sub-carrier PLL is locked to the incoming video source.
1470  * 0 Sub-carrier PLL is not locked.
1496 #define TW5864_INDIR_VIN_1(channel) (0x001 + channel * 0x010)  argument
1497 /* VCR signal indicator. Read-only. */
1499 /* Weak signal indicator 2. Read-only. */
1501 /* Weak signal indicator controlled by WKTH. Read-only. */
1505  * 0 = Non-standard signal
1506  * Read-only
1510  * 1 = Non-interlaced signal
1512  * Read-only
1524 #define TW5864_INDIR_VIN_2_HDELAY_XY_LO(channel) (0x002 + channel * 0x010)  argument
1526 #define TW5864_INDIR_VIN_3_HACTIVE_XY_LO(channel) (0x003 + channel * 0x010)  argument
1528 #define TW5864_INDIR_VIN_4_VDELAY_XY_LO(channel) (0x004 + channel * 0x010)  argument
1530 #define TW5864_INDIR_VIN_5_VACTIVE_XY_LO(channel) (0x005 + channel * 0x010)  argument
1532 #define TW5864_INDIR_VIN_6(channel) (0x006 + channel * 0x010)  argument
1559  * value from +36o (7Fh) to -36o (80h) with an increment of 2.8o. The 2 LSB has
1564 #define TW5864_INDIR_VIN_7_HUE(channel) (0x007 + channel * 0x010)  argument
1566 #define TW5864_INDIR_VIN_8(channel) (0x008 + channel * 0x010)  argument
1595 #define TW5864_INDIR_VIN_9_CNTRST(channel) (0x009 + channel * 0x010)  argument
1598  * These bits control the brightness. They have value of -128 to 127 in 2's
1602 #define TW5864_INDIR_VIN_A_BRIGHT(channel) (0x00a + channel * 0x010)  argument
1612 #define TW5864_INDIR_VIN_B_SAT_U(channel) (0x00b + channel * 0x010)  argument
1622 #define TW5864_INDIR_VIN_C_SAT_V(channel) (0x00c + channel * 0x010)  argument
1624 /* Read-only */
1625 #define TW5864_INDIR_VIN_D(channel) (0x00d + channel * 0x010)  argument
1627 /* Macrovision color stripe detection may be un-reliable */
1641 /* Read-only */
1642 #define TW5864_INDIR_VIN_E(channel) (0x00e + channel * 0x010)  argument
1645  * Read-only.
1683 #define TW5864_INDIR_VIN_F(channel) (0x00f + channel * 0x010)  argument
1687  * process. This bit is a self-clearing bit
1708 /* Use falling edge to sample VD1-VD4 from 54 MHz to 108 MHz */
1730  * 11 1.75
1736 /* [3:0] channel 0, [7:4] channel 1 */
1738 /* [3:0] channel 2, [7:4] channel 3 */
1746  * LAWMD Select u-Law/A-Law/PCM/SB data output format on ADATR and ADATM pin.
1749  * 2 u-Law output
1750  * 3 A-Law output
1761  * Enable the mute function for audio channel AINn when n is 0 to 3. It effects
1774  * ADATP signal is coming from external ADPCM decoder, instead of on-chip ADPCM
1820  * 1 Almost duty 50-50% clock output on ACLKR pin. If this mode is selected, two
1825 /* Playback ACLKP/ASYNP/ADATP input data MSB-LSB swapping */
1842  * 1 Add 1 ACLKP clock delay in ADATP input data. This is for left-justified
1847  * Select u-Law/A-Law/PCM/SB data input format on ADATP pin.
1850  * 2 u-Law input
1851  * 3 A-Law input
1869 #define TW5864_INDIR_IN_PIC_WIDTH(channel) (0x200 + 4 * channel)  argument
1870 #define TW5864_INDIR_IN_PIC_HEIGHT(channel) (0x201 + 4 * channel)  argument
1871 #define TW5864_INDIR_OUT_PIC_WIDTH(channel) (0x202 + 4 * channel)  argument
1872 #define TW5864_INDIR_OUT_PIC_HEIGHT(channel) (0x203 + 4 * channel)  argument
1882  * Interrupt status register from the front-end. Write "1" to each bit to clear
1884  * 15:0 Motion detection interrupt for channel 0 ~ 15
1885  * 31:16 Night detection interrupt for channel 0 ~ 15
1886  * 47:32 Blind detection interrupt for channel 0 ~ 15
1887  * 63:48 No video interrupt for channel 0 ~ 15
1888  * 79:64 Line mode underflow interrupt for channel 0 ~ 15
1889  * 95:80 Line mode overflow interrupt for channel 0 ~ 15
1898  * 15:0 Motion detection interrupt for channel 0 ~ 15
1899  * 31:16 Night detection interrupt for channel 0 ~ 15
1900  * 47:32 Blind detection interrupt for channel 0 ~ 15
1901  * 63:48 No video interrupt for channel 0 ~ 15
1902  * 79:64 Line mode underflow interrupt for channel 0 ~ 15
1903  * 95:80 Line mode overflow interrupt for channel 0 ~ 15
1910 /* [11:0]: Interrupt summary register for interrupts & interrupt mask from in
1923  * bit 11: interrupt occurs in 0x2e3 & 0x2eb
1928 /* valid value for channel is [0:15] */
1929 #define TW5864_INDIR_DETECTION_CTL0(channel) (0x300 + channel * 0x08)  argument
1957 #define TW5864_INDIR_DETECTION_CTL1(channel) (0x301 + channel * 0x08)  argument
1975 #define TW5864_INDIR_DETECTION_CTL2(channel) (0x302 + channel * 0x08)  argument
2000 #define TW5864_INDIR_DETECTION_CTL3(channel) (0x303 + channel * 0x08)  argument
2003  * Define the threshold of sub-cell number for motion detection.
2004  * 0 Motion is detected if 1 sub-cell has motion (More sensitive) (default)
2005  * 1 Motion is detected if 2 sub-cells have motion
2006  * 2 Motion is detected if 3 sub-cells have motion
2007  * 3 Motion is detected if 4 sub-cells have motion (Less sensitive)
2024 #define TW5864_INDIR_DETECTION_CTL4(channel) (0x304 + channel * 0x08)  argument
2042 #define TW5864_INDIR_DETECTION_CTL5(channel) (0x305 + channel * 0x08)  argument
2060  * [11:0] The base address of the motion detection buffer. This address is in
2067  * This controls the channel of the motion detection result shown in register
2072 /* [15:0] MD strobe has been performed at channel n (read only) */
2074 /* NO_VIDEO Detected from channel n (read only) */
2076 /* Motion Detected from channel n (read only) */
2078 /* Blind Detected from channel n (read only) */
2080 /* Night Detected from channel n (read only) */
2083 /* 192 bit motion flag of the channel specified by RGR_MOTION_SEL in 0x382 */
2088  * [9:0] The motion cell count of a specific channel selected by 0x382. This is
2097 /* 192 bit motion mask of the channel specified by MASK_CH_SEL in 0x3fe */
2101 /* [4:0] The channel selection to access masks in 0x3e0 ~ 0x3f7 */
2123 #define TW5864_INDIR_PV_VD_CK_POL_PV(channel) BIT(channel)  argument
2124 #define TW5864_INDIR_PV_VD_CK_POL_VD(channel) BIT(channel + 4)  argument