Lines Matching +full:channel +full:- +full:11
1 /* SPDX-License-Identifier: GPL-2.0+ */
26 * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
32 * Describes the format of a scatter-gather DMA descriptor for the PLX
33 * PCI 9080. All members are raw, little-endian register values that
35 * corresponding registers for the DMA channel.
37 * The DMA descriptors must be aligned on a 16-byte boundary. Bits 3:0
99 /* DMA Channel Priority */
101 #define PLX_MARBR_PRIO_DMA0 (BIT(19) * 1) /* DMA channel 0 has priority */
102 #define PLX_MARBR_PRIO_DMA1 (BIT(19) * 2) /* DMA channel 1 has priority */
137 /* Big Endian Byte Lane Mode - use most significant byte lanes */
141 /* DMA Channel 1 Big Endian Mode */
143 /* DMA Channel 0 Big Endian Mode */
145 /* DMA Channel N Big Endian Mode (N <= 1) */
189 #define PLX_LBRD_PFCOUNT(x) (BIT(11) * ((x) & 0xf))
190 #define PLX_LBRD_PFCOUNT_MASK GENMASK(14, 11)
191 #define PLX_LBRD_TO_PFCOUNT(r) (((r) & PLX_LBRD_PFCOUNT_MASK) >> 11)
212 /* Direct Slave PCI Write Mode - assert TRDY# when FIFO full (LBRD0 only) */
243 /* Direct Master PCI Read Mode - deassert IRDY when FIFO full */
254 #define PLX_DBPBAM_PFLIMIT BIT(11)
263 /* Remap of Local-to-PCI Space Into PCI Address Space */
282 #define PLX_DMCFGA_DEVNUM(x) (BIT(11) * ((x) & 0x1f))
283 #define PLX_DMCFGA_DEVNUM_MASK GENMASK(15, 11)
284 #define PLX_DMCFGA_TO_DEVNUM(r) (((r) & PLX_DMCFGA_DEVNUM_MASK) >> 11)
315 /* PCI-to-Local Doorbell Register */
318 /* Local-to-PCI Doorbell Register */
330 /* Mailbox Interrupt Enable (local bus interrupts on PCI write to MBOX0-3) */
339 #define PLX_INTCSR_PLIEN BIT(11)
342 /* PCI Doorbell Interrupt Active (read-only) */
344 /* PCI Abort Interrupt Active (read-only) */
346 /* Local Interrupt (LINTi#) Active (read-only) */
352 /* DMA Channel 0 Interrupt Enable */
354 /* DMA Channel 1 Interrupt Enable */
356 /* DMA Channel N Interrupt Enable (N <= 1) */
358 /* Local Doorbell Interrupt Active (read-only) */
360 /* DMA Channel 0 Interrupt Active (read-only) */
362 /* DMA Channel 1 Interrupt Active (read-only) */
364 /* DMA Channel N Interrupt Active (N <= 1) (read-only) */
366 /* BIST Interrupt Active (read-only) */
368 /* Direct Master Not Bus Master During Master Or Target Abort (read-only) */
370 /* DMA Channel 0 Not Bus Master During Master Or Target Abort (read-only) */
372 /* DMA Channel 1 Not Bus Master During Master Or Target Abort (read-only) */
374 /* DMA Channel N Not Bus Master During Master Or Target Abort (read-only) */
377 /* Target Abort Not Generated After 256 Master Retries (read-only) */
379 /* PCI Wrote Mailbox 0 (enabled if bit 3 set) (read-only) */
381 /* PCI Wrote Mailbox 1 (enabled if bit 3 set) (read-only) */
383 /* PCI Wrote Mailbox 2 (enabled if bit 3 set) (read-only) */
385 /* PCI Wrote Mailbox 3 (enabled if bit 3 set) (read-only) */
387 /* PCI Wrote Mailbox N (N <= 3) (enabled if bit 3 set) (read-only) */
408 #define PLX_CNTRL_CCRDM_MASK GENMASK(11, 8)
418 /* General Purpose Input (USERI) (read-only) */
426 /* Serial EEPROM Data Read Bit (EEDO (sic)) (read-only) */
428 /* Serial EEPROM Present (read-only) */
434 /* Local Init Status (read-only) */
446 /* PCI Permanent Configuration ID Register (hard-coded PLX vendor and device) */
449 /* Hard-coded ID for PLX PCI 9080 */
452 /* PCI Permanent Revision ID Register (hard-coded silicon revision) (8-bit). */
455 /* DMA Channel N Mode Register (N <= 1) */
481 #define PLX_DMAMODE_LACONST BIT(11)
486 /* DMA EOT Enable - enables EOT0# or EOT1# input pin */
488 /* DMA Stop Data Transfer Mode - 0:BLAST; 1:EOT asserted or DREQ deasserted */
490 /* DMA Clear Count Mode - count in descriptor cleared on completion */
492 /* DMA Channel Interrupt Select - 0:local bus interrupt; 1:PCI interrupt */
495 /* DMA Channel N PCI Address Register (N <= 1) */
500 /* DMA Channel N Local Address Register (N <= 1) */
505 /* DMA Channel N Transfer Size (Bytes) Register (N <= 1) (first 23 bits) */
510 /* DMA Channel N Descriptor Pointer Register (N <= 1) */
526 /* DMA Channel N Command/Status Register (N <= 1) (8-bit) */
531 /* Channel Enable */
533 /* Channel Start - write 1 to start transfer (write-only) */
535 /* Channel Abort - write 1 to abort transfer (write-only) */
537 /* Clear Interrupt - write 1 to clear DMA Channel Interrupt (write-only) */
539 /* Channel Done - transfer complete/inactive (read-only) */
553 /* DMA Channel 0 PCI-to-Local Almost Full (divided by 2, minus 1) */
557 /* DMA Channel 0 Local-to-PCI Almost Empty (divided by 2, minus 1) */
561 /* DMA Channel 0 Local-to-PCI Almost Full (divided by 2, minus 1) */
563 #define PLX_DMATHR_C0LPAF_MASK GENMASK(11, 8)
565 /* DMA Channel 0 PCI-to-Local Almost Empty (divided by 2, minus 1) */
569 /* DMA Channel 1 PCI-to-Local Almost Full (divided by 2, minus 1) */
573 /* DMA Channel 1 Local-to-PCI Almost Empty (divided by 2, minus 1) */
577 /* DMA Channel 1 Local-to-PCI Almost Full (divided by 2, minus 1) */
581 /* DMA Channel 1 PCI-to-Local Almost Empty (divided by 2, minus 1) */
597 /* Value of QSR after reset - disables I2O feature completely. */
602 * to pre-fetch data off of end-of-ram. Limit the size of
603 * memory so host-side accesses cannot occur.
609 * plx9080_abort_dma - Abort a PLX PCI 9080 DMA transfer
611 * @channel: DMA channel number (0 or 1).
613 * Aborts the DMA transfer on the channel, which must have been enabled
618 * -%ETIMEDOUT if timed out waiting for abort to complete.
620 static inline int plx9080_abort_dma(void __iomem *iobase, unsigned int channel) in plx9080_abort_dma() argument
627 dma_cs_addr = iobase + PLX_REG_DMACSR(channel); in plx9080_abort_dma()
640 return -ETIMEDOUT; in plx9080_abort_dma()
642 /* disable and abort channel */ in plx9080_abort_dma()
651 return -ETIMEDOUT; in plx9080_abort_dma()