Lines Matching +full:channel +full:- +full:11

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * Copyright 2019-2020 NXP
12 /* Channel Control Register */
33 /* Channel Image Control Register */
98 #define CHNL_IMG_CTRL_DEC_X_MASK				GENMASK(11, 10)
113 /* Channel Output Buffer Control Register */
136 /* Channel Image Configuration */
143 /* Channel Interrupt Enable Register */
153 /* Channel Status Register */
179 /* Channel Scale Factor Register */
186 /* Channel Scale Offset Register */
191 #define CHNL_SCALE_OFFSET_X_SCALE_MASK				GENMASK(11, 0)
193 /* Channel Crop Upper Left Corner Coordinate Register */
198 #define CHNL_CROP_ULC_Y_MASK					GENMASK(11, 0)
200 /* Channel Crop Lower Right Corner Coordinate Register */
205 #define CHNL_CROP_LRC_Y_MASK					GENMASK(11, 0)
207 /* Channel Color Space Conversion Coefficient Register 0 */
214 /* Channel Color Space Conversion Coefficient Register 1 */
221 /* Channel Color Space Conversion Coefficient Register 2 */
228 /* Channel Color Space Conversion Coefficient Register 3 */
235 /* Channel Color Space Conversion Coefficient Register 4 */
242 /* Channel Color Space Conversion Coefficient Register 5 */
249 /* Channel Alpha Value Register for ROI 0 */
255 /* Channel Upper Left Coordinate Register for ROI 0 */
260 #define CHNL_ROI_0_ULC_Y_MASK					GENMASK(11, 0)
262 /* Channel Lower Right Coordinate Register for ROI 0 */
267 #define CHNL_ROI_0_LRC_Y_MASK					GENMASK(11, 0)
269 /* Channel Alpha Value Register for ROI 1 */
275 /* Channel Upper Left Coordinate Register for ROI 1 */
280 #define CHNL_ROI_1_ULC_Y_MASK					GENMASK(11, 0)
282 /* Channel Lower Right Coordinate Register for ROI 1 */
287 #define CHNL_ROI_1_LRC_Y_MASK					GENMASK(11, 0)
289 /* Channel Alpha Value Register for ROI 2 */
295 /* Channel Upper Left Coordinate Register for ROI 2 */
300 #define CHNL_ROI_2_ULC_Y_MASK					GENMASK(11, 0)
302 /* Channel Lower Right Coordinate Register for ROI 2 */
307 #define CHNL_ROI_2_LRC_Y_MASK					GENMASK(11, 0)
309 /* Channel Alpha Value Register for ROI 3 */
315 /* Channel Upper Left Coordinate Register for ROI 3 */
320 #define CHNL_ROI_3_ULC_Y_MASK					GENMASK(11, 0)
322 /* Channel Lower Right Coordinate Register for ROI 3 */
327 #define CHNL_ROI_3_LRC_Y_MASK					GENMASK(11, 0)
328 /* Channel RGB or Luma (Y) Output Buffer 1 Address */
331 /* Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address */
334 /* Channel Chroma (V/Cr) Output Buffer 1 Address */
337 /* Channel Output Buffer Pitch */
342 /* Channel Input Buffer Address */
345 /* Channel Input Buffer Pitch */
352 /* Channel Memory Read Control */
374 /* Channel RGB or Luma (Y) Output Buffer 2 Address */
377 /* Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address  */
380 /* Channel Chroma (V/Cr) Output Buffer 2 Address   */
383 /* Channel scale image config */
390 /* Channel Flow Control Register */
397 /* Channel Output Y-Buffer 1 Extended Address Bits */
400 /* Channel Output U-Buffer 1 Extended Address Bits */
403 /* Channel Output V-Buffer 1 Extended Address Bits */
406 /* Channel Output Y-Buffer 2 Extended Address Bits */
409 /* Channel Output U-Buffer 2 Extended Address Bits */
412 /* Channel Output V-Buffer 2 Extended Address Bits */
415 /* Channel Input Buffer Extended Address Bits */