Home
last modified time | relevance | path

Searched +full:big +full:- +full:endian +full:- +full:regs (Results 1 – 25 of 138) sorted by relevance

123456

/linux/Documentation/devicetree/bindings/dma/
H A Dfsl-qdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl-qdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 - const: fsl,ls1021a-qdma
16 - items:
17 - enum:
18 - fsl,ls1028a-qdma
19 - fsl,ls1043a-qdma
[all …]
/linux/drivers/usb/host/
H A Dohci.h1 /* SPDX-License-Identifier: GPL-1.0+ */
6 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
27 /* first fields are hardware-specified */
49 struct ed *ed_prev; /* for non-interrupt EDs */
53 /* create --> IDLE --> OPER --> ... --> IDLE --> destroy
54 * usually: OPER --> UNLINK --> (IDLE | OPER) --> ...
76 ((int) (ohci->wdh_cnt - ed->takeback_wdh_cnt) >= 0)
89 /* first fields are hardware-specified */
124 * big-endian PPC hardware that's the second entry.
132 struct td *td_hash; /* dma-->td hashtable */
[all …]
H A Duhci-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
61 #define USBPORTSC_DMINUS 0x0020 /* D- high (line status) */
80 /* PCI Intel-specific resume-enable register */
97 /* When no queues need Full-Speed Bandwidth Reclamation,
110 * To facilitate the strongest possible byte-order checking from "sparse"
127 * with each endpoint, and qh->element (updated by the HC) is either:
128 * - the next unprocessed TD in the endpoint's queue, or
129 * - UHCI_PTR_TERM (when there's no more traffic for this endpoint).
133 * place. Then qh->element is UHCI_PTR_TERM.
135 * In the schedule, qh->link maintains a list of QHs seen by the HC:
[all …]
/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
12 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "arm,cortex-a7";
[all …]
/linux/Documentation/devicetree/bindings/mips/cavium/
H A Ductl.txt4 - compatible: "cavium,octeon-6335-uctl"
8 - reg: The base address of the UCTL register bank.
10 - #address-cells: Must be <2>.
12 - #size-cells: Must be <2>.
14 - ranges: Empty to signify direct mapping of the children.
16 - refclk-frequency: A single cell containing the reference clock
19 - refclk-type: A string describing the reference clock connection
24 compatible = "cavium,octeon-6335-uctl";
27 #address-cells = <2>;
28 #size-cells = <2>;
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <1>;
[all …]
H A Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
[all …]
H A Dfsl-ls1012a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1012A family SoC.
6 * Copyright 2019-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
23 rtic-a = &rtic_a;
[all …]
/linux/drivers/dma/
H A Dfsl-edma-common.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
11 #include <linux/dma-mapping.h>
15 #include "fsl-edma-common.h"
49 spin_lock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
51 if (!fsl_chan->edesc) { in fsl_edma_tx_chan_handler()
53 spin_unlock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
57 if (!fsl_chan->edesc->iscyclic) { in fsl_edma_tx_chan_handler()
58 list_del(&fsl_chan->edesc->vdesc.node); in fsl_edma_tx_chan_handler()
59 vchan_cookie_complete(&fsl_chan->edesc->vdesc); in fsl_edma_tx_chan_handler()
[all …]
H A Dfsl-edma-common.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
9 #include <linux/dma-direction.h>
11 #include "virt-dma.h"
245 struct edma_regs regs; member
252 return fsl_chan->edma->drvdata->flags; in fsl_edma_drvflags()
256 _Generic(((_tcd)->__name), \
257 __iomem __le64 : edma_readq(chan->edma, &(_tcd)->__name), \
258 __iomem __le32 : edma_readl(chan->edma, &(_tcd)->__name), \
259 __iomem __le16 : edma_readw(chan->edma, &(_tcd)->__name) \
[all …]
/linux/arch/mips/include/asm/sgi/
H A Dhpc3.h36 /* The set of regs for each HPC3 PBUS DMA channel. */
40 u32 _unused0[0x1000/4 - 2]; /* padding */
48 #define HPC3_PDMACTRL_SEL 0x00000002 /* little endian transfer */
54 #define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */
58 u32 _unused1[0x1000/4 - 1]; /* padding */
65 u32 _unused0[0x1000/4 - 2]; /* padding */
73 #define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
89 #define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
100 #define HPC3_SPCFG_HW 0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
105 u32 _unused1[0x1000/4 - 6]; /* padding */
[all …]
/linux/drivers/phy/broadcom/
H A Dphy-brcm-usb-init.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2014-2017 Broadcom
60 void __iomem *regs[BRCM_REGS_MAX]; member
84 * bus endianness (i.e., big-endian CPU + big endian bus ==> native in brcm_usb_readl()
85 * endian I/O). in brcm_usb_readl()
87 * Other architectures (e.g., ARM) either do not support big endian, or in brcm_usb_readl()
88 * else leave I/O in little endian mode. in brcm_usb_readl()
117 if (ini->ops->init_ipp) in brcm_usb_init_ipp()
118 ini->ops->init_ipp(ini); in brcm_usb_init_ipp()
123 if (ini->ops->init_common) in brcm_usb_init_common()
[all …]
/linux/drivers/gpio/
H A Dgpio-mpc8xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
38 void __iomem *regs; member
49 * This hardware has a big endian bit assignment such that GPIO line 0 is
55 return BIT(31 - offset); in mpc_pin2mask()
69 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); in mpc8572_gpio_get()
70 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; in mpc8572_gpio_get()
71 out_shadow = gc->bgpio_data & out_mask; in mpc8572_gpio_get()
82 return -EINVAL; in mpc5121_gpio_dir_out()
84 return mpc8xxx_gc->direction_output(gc, gpio, val); in mpc5121_gpio_dir_out()
93 return -EINVAL; in mpc5125_gpio_dir_out()
[all …]
/linux/Documentation/bpf/standardization/
H A Dinstruction-set.rst27 BCP 14 `<https://www.rfc-editor.org/info/rfc2119>`_
28 `<https://www.rfc-editor.org/info/rfc8174>`_
38 -----
51 .. table:: Meaning of bit-width notation
63 For example, `u32` is a type whose valid values are all the 32-bit unsigned
64 numbers and `s16` is a type whose valid values are all the 16-bit signed
68 ---------
70 The following byteswap functions are direction-agnostic. That is,
74 * be16: Takes an unsigned 16-bit number and converts it between
75 host byte order and big-endian
[all …]
/linux/arch/arm64/include/asm/
H A Dsyscall.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 typedef long (*syscall_fn_t)(const struct pt_regs *regs);
21 struct pt_regs *regs) in syscall_get_nr() argument
23 return regs->syscallno; in syscall_get_nr()
27 struct pt_regs *regs) in syscall_rollback() argument
29 regs->regs[0] = regs->orig_x0; in syscall_rollback()
33 struct pt_regs *regs) in syscall_get_return_value() argument
35 unsigned long val = regs->regs[0]; in syscall_get_return_value()
44 struct pt_regs *regs) in syscall_get_error() argument
46 unsigned long error = syscall_get_return_value(task, regs); in syscall_get_error()
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dfsl,layerscape-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
16 which is used to describe the PLL settings at the time of chip-reset.
26 - enum:
27 - fsl,ls1012a-pcie
28 - fsl,ls1021a-pcie
29 - fsl,ls1028a-pcie
[all …]
/linux/include/video/
H A Dsstfb.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/drivers/video/sstfb.h -- voodoo graphics frame buffer
105 # define LFB_WORD_SWIZZLE_WR BIT(11) /* enable write-wordswap (big-endian) */
106 # define LFB_BYTE_SWIZZLE_WR BIT(12) /* enable write-byteswap (big-endian) */
108 # define LFB_WORD_SWIZZLE_RD BIT(15) /* enable read-wordswap (big-endian) */
109 # define LFB_BYTE_SWIZZLE_RD BIT(16) /* enable read-byteswap (big-endian) */
192 # define BLT_SCR2SCR_BITBLT 0 /* Screen-to-Screen BitBLT */
193 # define BLT_CPU2SCR_BITBLT 1 /* CPU-to-screen BitBLT */
195 # define BLT_16BPP_FMT 2 /* 16 BPP (5-6-5 RGB) */
196 #define BLTDATA 0x02fc /* BitBLT data for CPU-to-Screen BitBLTs */
[all …]
/linux/drivers/base/regmap/
H A Dregmap-mmio.c1 // SPDX-License-Identifier: GPL-2.0
3 // Register map access API - MMIO support
18 void __iomem *regs; member
39 return -EINVAL; in regmap_mmio_regbits_check()
59 return -EINVAL; in regmap_mmio_get_min_stride()
69 writeb(val, ctx->regs + reg); in regmap_mmio_write8()
76 writeb_relaxed(val, ctx->regs + reg); in regmap_mmio_write8_relaxed()
82 iowrite8(val, ctx->regs + reg); in regmap_mmio_iowrite8()
89 writew(val, ctx->regs + reg); in regmap_mmio_write16le()
96 writew_relaxed(val, ctx->regs + reg); in regmap_mmio_write16le_relaxed()
[all …]
/linux/drivers/pci/controller/
H A Dpci-ixp4xx.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on the IXP4xx arch/arm/mach-ixp4xx/common-pci.c driver
9 * Copyright (C) 2003 Greg Ungerer <gerg@linux-m68k.org>
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
15 * - Test IO-space access
16 * - DMA support
113 * operates in big-endian or little-endian mode. That means that
114 * readl() and writel() that always use little-endian access
116 * when used in big-endian mode. The accesses to the individual
117 * PCI devices on the other hand, are always little-endian and
[all …]
/linux/arch/arm64/lib/
H A Dstrncmp.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2013-2022, Arm Limited.
6 * https://github.com/ARM-software/optimized-routines/blob/189dfefe37d54c5b/string/aarch64/strncmp.S
14 * ARMv8-a, AArch64.
48 /* Define endian dependent shift operations.
49 On big-endian early bytes are at MSB and on little-endian LSB.
70 /* NUL detection works on the principle that (X - 1) & (~X) & 0x80
71 (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
81 eor diff, data1, data2 /* Non-zero if differences found. */
83 bics has_nul, tmp1, tmp2 /* Non-zero if NUL terminator. */
[all …]
/linux/drivers/scsi/cxlflash/
H A Dsislite.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
24 * except for SCSI CDB which remains big endian per SCSI standards.
49 * 0x1 -> port#0 can be selected,
50 * 0x2 -> port#1 can be selected.
65 #define SISL_MSI_ASYNC_ERROR 3 /* master only - for AFU async error */
70 u8 cdb[16]; /* must be in big endian */
147 #define SISL_FC_RC_NOLOGI 0x54 /* port not logged in, in-flight cmds */
150 #define SISL_FC_RC_LINKDOWN 0x57 /* link down, in-flight cmds */
222 /* MMIO space is required to support only 64-bit access */
225 * This AFU has two mechanisms to deal with endian-ness.
[all …]
/linux/arch/powerpc/include/asm/
H A Dptrace.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 * this should only contain volatile regs
9 * since we can keep non-volatile in the thread_struct
24 #include <asm/asm-const.h>
100 // Always displays as "REGS" in memory dumps
111 * pointer. This is 288 in the 64-bit big-endian ELF ABI, and 512 in
112 * the new ELFv2 little-endian ABI, so we allow the larger amount.
114 * For kernel code we allow a 288-byte redzone, in order to conserve
139 #define STACK_INT_FRAME_MARKER (STACK_FRAME_MIN_SIZE - 16)
156 #define STACK_INT_FRAME_MARKER (STACK_FRAME_MIN_SIZE - 8)
[all …]
/linux/drivers/usb/fotg210/
H A Dfotg210-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/usb/ehci-dbgp.h>
14 * To facilitate the strongest possible byte-order checking from "sparse"
33 /* fotg210_hcd->lock guards shared data against other CPUs:
59 * ehci-timer.c) in parallel with this list.
89 struct fotg210_regs __iomem *regs; member
152 /* which ports have the change-suspend feature turned on */
161 /* per-HC memory pools (could be per-bus, but ...) */
193 return (struct fotg210_hcd *)(hcd->hcd_priv); in hcd_to_fotg210()
200 /*-------------------------------------------------------------------------*/
[all …]
/linux/tools/testing/selftests/arm64/fp/
H A Dsve-ptrace.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015-2021 ARM Limited.
68 #define VL_TESTS (((TEST_VQ_MAX - SVE_VQ_MIN) + 1) * 4)
84 if (ptrace(PTRACE_TRACEME, -1, NULL, NULL)) in do_child()
135 if (ptrace(PTRACE_GETREGSET, pid, type->regset, &iov)) in get_sve()
139 if (sve->size <= sz) in get_sve()
142 sz = sve->siz in get_sve()
[all...]
/linux/drivers/memory/
H A Dbrcmstb_dpfe.c1 // SPDX-License-Identifier: GPL-2.0-only
21 * - LE kernel + LE firmware image (the most common case)
22 * - LE kernel + BE firmware image
23 * - BE kernel + LE firmware image
24 * - BE kernel + BE firmware image
26 * The DPCU always runs in big endian mode. The firmware image, however, can
28 * always in little endian.
38 #define DRVNAME "brcmstb-dpfe"
48 #define DRAM_MSG_ADDR_MASK ((1UL << DRAM_MSG_TYPE_OFFSET) - 1)
50 (BITS_PER_LONG - DRAM_MSG_TYPE_OFFSET)) - 1)
[all …]

123456