1 /* SPDX-License-Identifier: GPL-2.0 */
61 #define   USBPORTSC_DMINUS	0x0020	/* D- high (line status) */
80 /* PCI Intel-specific resume-enable register */
97 /* When no queues need Full-Speed Bandwidth Reclamation,
110  * To facilitate the strongest possible byte-order checking from "sparse"
127  * with each endpoint, and qh->element (updated by the HC) is either:
128  *   - the next unprocessed TD in the endpoint's queue, or
129  *   - UHCI_PTR_TERM (when there's no more traffic for this endpoint).
133  * place.  Then qh->element is UHCI_PTR_TERM.
135  * In the schedule, qh->link maintains a list of QHs seen by the HC:
136  *     skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ...
138  * qh->node is the software equivalent of qh->link.  The differences
139  * are that the software list is doubly-linked and QHs in the UNLINKING
167 					/* Next urb->iso_frame_desc entry */
171 	short phase;			/* Between 0 and period-1 */
191 #define qh_element(qh)		READ_ONCE((qh)->element)
194 				cpu_to_hc32((uhci), (qh)->dma_handle))
217 #define TD_CTRL_ACTLEN_MASK	0x7FF	/* actual length, encoded as n - 1 */
222 			TD_CTRL_ACTLEN_MASK)	/* 1-based */
227 #define td_token(uhci, td)	hc32_to_cpu((uhci), (td)->token)
232 #define TD_TOKEN_EXPLEN_MASK	0x7FF	/* expected length, encoded as n-1 */
235 #define uhci_explen(len)	((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \
252  * the hardware words are 16-byte aligned, and we can have any amount of
255  * td->link points to either another TD (not necessarily for the same urb or
279 						READ_ONCE((td)->status))
281 #define LINK_TO_TD(uhci, td)		(cpu_to_hc32((uhci), (td)->dma_handle))
292  * Asynchronous QHs (low-speed control, full-speed control, and bulk)
293  * go onto the period-1 interrupt list, since they all get accessed on
306  * dev 5 low-speed control QH
310  * There is a special terminating QH used to keep full-speed bandwidth
311  * reclamation active when no full-speed control or bulk QHs are linked
335 #define SKEL_INDEX(exponent)	(9 - exponent)
388 	void __iomem *regs;  member
416 						   Resume-Detect interrupts
428 	unsigned int big_endian_mmio:1;		/* Big endian registers */
429 	unsigned int big_endian_desc:1;		/* Big endian descriptors */
433 	unsigned long port_c_suspend;		/* Bit-arrays of ports */
439 	int rh_numports;			/* Number of root-hub ports */
463 	return (struct uhci_hcd *) (hcd->hcd_priv);  in hcd_to_uhci()
470 #define uhci_dev(u)	(uhci_to_hcd(u)->self.controller)
473 #define uhci_frame_before_eq(f1, f2)	(0 <= (int) ((f2) - (f1)))
477  *	Private per-URB data
499 	return IS_ENABLED(CONFIG_USB_UHCI_ASPEED) && uhci->is_aspeed;  in uhci_is_aspeed()
504  * controller I/O registers are mapped into PCI I/O space. For non-PCI hosts
520 	return inl(uhci->io_addr + reg);  in uhci_readl()
525 	outl(val, uhci->io_addr + reg);  in uhci_writel()
530 	return inw(uhci->io_addr + reg);  in uhci_readw()
535 	outw(val, uhci->io_addr + reg);  in uhci_writew()
540 	return inb(uhci->io_addr + reg);  in uhci_readb()
545 	outb(val, uhci->io_addr + reg);  in uhci_writeb()
549 /* Support non-PCI host controllers */
551 /* Support PCI and non-PCI host controllers */
552 #define uhci_has_pci_registers(u)	((u)->io_addr != 0)
554 /* Support non-PCI host controllers only */
559 /* Support (non-PCI) big endian host controllers */
560 #define uhci_big_endian_mmio(u)		((u)->big_endian_mmio)
598 		return UHCI_IN(inl(uhci->io_addr + reg));  in uhci_readl()
600 		return readl(uhci->regs + uhci_aspeed_reg(reg));  in uhci_readl()
603 		return readl_be(uhci->regs + reg);  in uhci_readl()
606 		return readl(uhci->regs + reg);  in uhci_readl()
612 		UHCI_OUT(outl(val, uhci->io_addr + reg));  in uhci_writel()
614 		writel(val, uhci->regs + uhci_aspeed_reg(reg));  in uhci_writel()
617 		writel_be(val, uhci->regs + reg);  in uhci_writel()
620 		writel(val, uhci->regs + reg);  in uhci_writel()
626 		return UHCI_IN(inw(uhci->io_addr + reg));  in uhci_readw()
628 		return readl(uhci->regs + uhci_aspeed_reg(reg));  in uhci_readw()
631 		return readw_be(uhci->regs + reg);  in uhci_readw()
634 		return readw(uhci->regs + reg);  in uhci_readw()
640 		UHCI_OUT(outw(val, uhci->io_addr + reg));  in uhci_writew()
642 		writel(val, uhci->regs + uhci_aspeed_reg(reg));  in uhci_writew()
645 		writew_be(val, uhci->regs + reg);  in uhci_writew()
648 		writew(val, uhci->regs + reg);  in uhci_writew()
654 		return UHCI_IN(inb(uhci->io_addr + reg));  in uhci_readb()
656 		return readl(uhci->regs + uhci_aspeed_reg(reg));  in uhci_readb()
659 		return readb_be(uhci->regs + reg);  in uhci_readb()
662 		return readb(uhci->regs + reg);  in uhci_readb()
668 		UHCI_OUT(outb(val, uhci->io_addr + reg));  in uhci_writeb()
670 		writel(val, uhci->regs + uhci_aspeed_reg(reg));  in uhci_writeb()
673 		writeb_be(val, uhci->regs + reg);  in uhci_writeb()
676 		writeb(val, uhci->regs + reg);  in uhci_writeb()
683  * The GRLIB GRUSBHC controller can use big endian format for its descriptors.
685  * UHCI controllers accessed through PCI work normally (little-endian
686  * everywhere), so we don't bother supporting a BE-only mode.
689 #define uhci_big_endian_desc(u)		((u)->big_endian_desc)