Lines Matching +full:big +full:- +full:endian +full:- +full:regs
1 // SPDX-License-Identifier: GPL-2.0-only
38 void __iomem *regs; member
49 * This hardware has a big endian bit assignment such that GPIO line 0 is
55 return BIT(31 - offset); in mpc_pin2mask()
69 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); in mpc8572_gpio_get()
70 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; in mpc8572_gpio_get()
71 out_shadow = gc->bgpio_data & out_mask; in mpc8572_gpio_get()
82 return -EINVAL; in mpc5121_gpio_dir_out()
84 return mpc8xxx_gc->direction_output(gc, gpio, val); in mpc5121_gpio_dir_out()
93 return -EINVAL; in mpc5125_gpio_dir_out()
95 return mpc8xxx_gc->direction_output(gc, gpio, val); in mpc5125_gpio_dir_out()
102 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS) in mpc8xxx_gpio_to_irq()
103 return irq_create_mapping(mpc8xxx_gc->irq, offset); in mpc8xxx_gpio_to_irq()
105 return -ENXIO; in mpc8xxx_gpio_to_irq()
111 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_gpio_irq_cascade()
115 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER) in mpc8xxx_gpio_irq_cascade()
116 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR); in mpc8xxx_gpio_irq_cascade()
118 generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i); in mpc8xxx_gpio_irq_cascade()
127 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_unmask()
132 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_unmask()
134 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, in mpc8xxx_irq_unmask()
135 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) in mpc8xxx_irq_unmask()
138 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_unmask()
145 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_mask()
148 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_mask()
150 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, in mpc8xxx_irq_mask()
151 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) in mpc8xxx_irq_mask()
154 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_mask()
162 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_ack()
164 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, in mpc8xxx_irq_ack()
171 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_set_type()
177 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
178 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, in mpc8xxx_irq_set_type()
179 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) in mpc8xxx_irq_set_type()
181 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
185 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
186 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, in mpc8xxx_irq_set_type()
187 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) in mpc8xxx_irq_set_type()
189 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
193 return -EINVAL; in mpc8xxx_irq_set_type()
202 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc512x_irq_set_type()
209 reg = mpc8xxx_gc->regs + GPIO_ICR; in mpc512x_irq_set_type()
210 shift = (15 - gpio) * 2; in mpc512x_irq_set_type()
212 reg = mpc8xxx_gc->regs + GPIO_ICR2; in mpc512x_irq_set_type()
213 shift = (15 - (gpio % 16)) * 2; in mpc512x_irq_set_type()
219 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
220 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) in mpc512x_irq_set_type()
222 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
227 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
228 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) in mpc512x_irq_set_type()
230 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
234 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
235 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))); in mpc512x_irq_set_type()
236 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
240 return -EINVAL; in mpc512x_irq_set_type()
247 .name = "mpc8xxx-gpio",
260 irq_set_chip_data(irq, h->host_data); in mpc8xxx_gpio_irq_map()
296 { .compatible = "fsl,mpc8314-gpio", },
297 { .compatible = "fsl,mpc8349-gpio", },
298 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
299 { .compatible = "fsl,mpc8610-gpio", },
300 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
301 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
302 { .compatible = "fsl,pq3-gpio", },
303 { .compatible = "fsl,ls1028a-gpio", },
304 { .compatible = "fsl,ls1088a-gpio", },
305 { .compatible = "fsl,qoriq-gpio", },
313 struct device *dev = &pdev->dev; in mpc8xxx_probe()
320 return -ENOMEM; in mpc8xxx_probe()
324 raw_spin_lock_init(&mpc8xxx_gc->lock); in mpc8xxx_probe()
326 mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0); in mpc8xxx_probe()
327 if (IS_ERR(mpc8xxx_gc->regs)) in mpc8xxx_probe()
328 return PTR_ERR(mpc8xxx_gc->regs); in mpc8xxx_probe()
330 gc = &mpc8xxx_gc->gc; in mpc8xxx_probe()
331 gc->parent = dev; in mpc8xxx_probe()
333 if (device_property_read_bool(dev, "little-endian")) { in mpc8xxx_probe()
334 ret = bgpio_init(gc, dev, 4, mpc8xxx_gc->regs + GPIO_DAT, in mpc8xxx_probe()
335 NULL, NULL, mpc8xxx_gc->regs + GPIO_DIR, in mpc8xxx_probe()
339 dev_dbg(dev, "GPIO registers are LITTLE endian\n"); in mpc8xxx_probe()
341 ret = bgpio_init(gc, dev, 4, mpc8xxx_gc->regs + GPIO_DAT, in mpc8xxx_probe()
342 NULL, NULL, mpc8xxx_gc->regs + GPIO_DIR, in mpc8xxx_probe()
347 dev_dbg(dev, "GPIO registers are BIG endian\n"); in mpc8xxx_probe()
350 mpc8xxx_gc->direction_output = gc->direction_output; in mpc8xxx_probe()
360 if (devtype->irq_set_type) in mpc8xxx_probe()
361 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type; in mpc8xxx_probe()
363 if (devtype->gpio_dir_out) in mpc8xxx_probe()
364 gc->direction_output = devtype->gpio_dir_out; in mpc8xxx_probe()
365 if (devtype->gpio_get) in mpc8xxx_probe()
366 gc->get = devtype->gpio_get; in mpc8xxx_probe()
368 gc->to_irq = mpc8xxx_gpio_to_irq; in mpc8xxx_probe()
378 if (device_is_compatible(dev, "fsl,qoriq-gpio") || in mpc8xxx_probe()
379 device_is_compatible(dev, "fsl,ls1028a-gpio") || in mpc8xxx_probe()
380 device_is_compatible(dev, "fsl,ls1088a-gpio") || in mpc8xxx_probe()
382 gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff); in mpc8xxx_probe()
384 gc->bgpio_data = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & in mpc8xxx_probe()
385 gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); in mpc8xxx_probe()
395 mpc8xxx_gc->irqn = platform_get_irq(pdev, 0); in mpc8xxx_probe()
396 if (mpc8xxx_gc->irqn < 0) in mpc8xxx_probe()
397 return mpc8xxx_gc->irqn; in mpc8xxx_probe()
399 mpc8xxx_gc->irq = irq_domain_create_linear(fwnode, in mpc8xxx_probe()
404 if (!mpc8xxx_gc->irq) in mpc8xxx_probe()
408 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff); in mpc8xxx_probe()
409 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0); in mpc8xxx_probe()
411 ret = devm_request_irq(dev, mpc8xxx_gc->irqn, in mpc8xxx_probe()
413 IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade", in mpc8xxx_probe()
417 mpc8xxx_gc->irqn, ret); in mpc8xxx_probe()
427 irq_domain_remove(mpc8xxx_gc->irq); in mpc8xxx_probe()
435 if (mpc8xxx_gc->irq) { in mpc8xxx_remove()
436 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL); in mpc8xxx_remove()
437 irq_domain_remove(mpc8xxx_gc->irq); in mpc8xxx_remove()
445 if (mpc8xxx_gc->irqn && device_may_wakeup(dev)) in mpc8xxx_suspend()
446 enable_irq_wake(mpc8xxx_gc->irqn); in mpc8xxx_suspend()
455 if (mpc8xxx_gc->irqn && device_may_wakeup(dev)) in mpc8xxx_resume()
456 disable_irq_wake(mpc8xxx_gc->irqn); in mpc8xxx_resume()
476 .name = "gpio-mpc8xxx",