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/freebsd/sys/arm/freescale/vybrid/
H A Dvf_iomuxc.h31 #define IOMUXC_PTA6 0x000 /* Software MUX Pad Control Register 0 */
32 #define IOMUXC_PTA8 0x004 /* Software MUX Pad Control Register 1 */
33 #define IOMUXC_PTA9 0x008 /* Software MUX Pad Control Register 2 */
34 #define IOMUXC_PTA10 0x00C /* Software MUX Pad Control Register 3 */
35 #define IOMUXC_PTA11 0x010 /* Software MUX Pad Control Register 4 */
36 #define IOMUXC_PTA12 0x014 /* Software MUX Pad Control Register 5 */
37 #define IOMUXC_PTA16 0x018 /* Software MUX Pad Control Register 6 */
38 #define IOMUXC_PTA17 0x01C /* Software MUX Pad Control Register 7 */
39 #define IOMUXC_PTA18 0x020 /* Software MUX Pad Control Register 8 */
40 #define IOMUXC_PTA19 0x024 /* Software MUX Pad Control Register 9 */
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h46 /// Convenient type to represent either a register class or a register bank.
51 /// registers, including vreg register classes, use/def chains for registers,
61 virtual void MRI_NoteNewVirtualRegister(Register Reg) = 0;
62 virtual void MRI_NoteCloneVirtualRegister(Register NewReg, in MRI_NoteCloneVirtualRegister()
63 Register SrcReg) { in MRI_NoteCloneVirtualRegister()
75 /// VRegInfo - Information we keep for each virtual register.
77 /// Each element in this list contains the register class of the vreg and the
78 /// start of the use/def list for the register.
94 /// Contains the updated callee saved register list.
95 /// As opposed to the static list defined in register info,
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H A DRegister.h1 //===-- llvm/CodeGen/Register.h ---------------------------------*- C++ -*-===//
19 class Register {
23 constexpr Register(unsigned Val = 0) : Reg(Val) {} in Reg()
24 constexpr Register(MCRegister Val) : Reg(Val.id()) {} in Register() function
26 // Register numbers can represent physical registers, virtual registers, and
29 // 0 Not a register, can be used as a sentinel.
44 return Register::FirstStackSlot <= Reg && Reg < Register::VirtualRegFlag; in isStack()
47 /// Convert a non-negative frame index to a stack slot register value.
48 static Register index2StackSlot(int FI) { in index2StackSlot()
50 return Register(FI + Register::FirstStackSlot); in index2StackSlot()
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H A DVirtRegMap.h1 //===- llvm/CodeGen/VirtRegMap.h - Virtual Register Map ---------*- C++ -*-===//
9 // This file implements a virtual register map. This maps virtual registers to
11 // updated by a register allocator and then used by a machine code rewriter that
12 // adds spill code and rewrites virtual into physical register references.
41 /// Virt2PhysMap - This is a virtual to physical register
42 /// mapping. Each virtual register is required to have an entry in
43 /// it; even spilled virtual registers (the register mapped to a
44 /// spilled register is the temporary used to load it from the
48 /// Virt2StackSlotMap - This is virtual register to stack slot
49 /// mapping. Each spilled virtual register has an entry in it
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H A DTargetRegisterInfo.h1 //==- CodeGen/TargetRegisterInfo.h - Target Register Information -*- C++ -*-==//
10 // target machines register file. This information is used for a variety of
11 // purposed, especially register allocation.
55 /// Classes with a higher priority value are assigned first by register
66 /// Whether a combination of subregisters can cover every register in the
73 /// Return the register class ID number.
88 /// Return the specified register in the class.
93 /// Return true if the specified register is included in this register class.
95 bool contains(Register Reg) const { in contains()
104 bool contains(Register Reg1, Register Reg2) const { in contains()
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H A DFastISel.h91 Register ResultReg;
96 SmallVector<Register, 16> OutRegs;
98 SmallVector<Register, 4> InRegs;
202 DenseMap<const Value *, Register> LocalValueMap;
267 /// Create a virtual register and arrange for it to be assigned the
269 Register getRegForValue(const Value *V);
272 /// register. It may be defined by instructions across blocks or defined
274 Register lookUpRegForValue(const Value *V);
278 Register getRegForGEPIndex(MVT PtrVT, const Value *Idx);
351 virtual Register fastEmit_(MVT VT, MVT RetVT, unsigned Opcode);
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dmc13xxx.txt16 - leds : Contain the led nodes and initial register values in property
17 "led-control". Number of register depends of used IC, for MC13783 is 6,
55 sw1a : regulator SW1A (register 24, bit 0)
56 sw1b : regulator SW1B (register 25, bit 0)
57 sw2a : regulator SW2A (register 26, bit 0)
58 sw2b : regulator SW2B (register 27, bit 0)
59 sw3 : regulator SW3 (register 29, bit 20)
60 vaudio : regulator VAUDIO (register 32, bit 0)
61 viohi : regulator VIOHI (register 32, bit 3)
62 violo : regulator VIOLO (register 32, bit 6)
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/freebsd/sys/contrib/device-tree/Bindings/cache/
H A Dqcom,llcc.yaml84 - description: LLCC0 base register region
99 - description: LLCC0 base register region
100 - description: LLCC1 base register region
101 - description: LLCC2 base register region
102 - description: LLCC3 base register region
103 - description: LLCC4 base register region
104 - description: LLCC5 base register region
105 - description: LLCC6 base register region
106 - description: LLCC7 base register region
107 - description: LLCC8 base register region
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/freebsd/sys/dev/tsec/
H A Dif_tsecreg.h29 #define TSEC_REG_ID 0x000 /* Controller ID register #1. */
30 #define TSEC_REG_ID2 0x004 /* Controller ID register #2. */
33 #define TSEC_REG_IEVENT 0x010 /* Interrupt event register */
34 #define TSEC_REG_IMASK 0x014 /* Interrupt mask register */
35 #define TSEC_REG_EDIS 0x018 /* Error disabled register */
36 #define TSEC_REG_ECNTRL 0x020 /* Ethernet control register */
37 #define TSEC_REG_MINFLR 0x024 /* Minimum frame length register */
38 #define TSEC_REG_PTV 0x028 /* Pause time value register */
39 #define TSEC_REG_DMACTRL 0x02c /* DMA control register */
40 #define TSEC_REG_TBIPA 0x030 /* TBI PHY address register */
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/freebsd/sys/arm/include/
H A Dsysreg.h31 * Note that when register r0 is hard-coded in these definitions it means the
32 * cp15 operation neither reads nor writes the register, and r0 is used only
33 * because some syntatically-valid register name has to appear at that point to
43 #define CP14_DBGDIDR(rr) p14, 0, rr, c0, c0, 0 /* Debug ID Register */
44 #define CP14_DBGDSCRext_V6(rr) p14, 0, rr, c0, c1, 0 /* Debug Status and Ctrl Register v6 */
45 #define CP14_DBGDSCRext_V7(rr) p14, 0, rr, c0, c2, 2 /* Debug Status and Ctrl Register v7 */
46 #define CP14_DBGVCR(rr) p14, 0, rr, c0, c7, 0 /* Vector Catch Register */
47 #define CP14_DBGOSLAR(rr) p14, 0, rr, c1, c0, 4 /* OS Lock Access Register */
48 #define CP14_DBGOSLSR(rr) p14, 0, rr, c1, c1, 4 /* OS Lock Status Register */
49 #define CP14_DBGOSDLR(rr) p14, 0, rr, c1, c3, 4 /* OS Double Lock Register */
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/freebsd/sys/dev/aic7xxx/
H A Daic79xx.reg2 * Aic79xx register and scratch ram definitions.
48 /* Register window Modes */
83 * as the source and destination of any register accesses in our
84 * register window.
86 register MODE_PTR {
100 register INTSTAT {
117 register SEQINTCODE {
196 register CLRINT {
210 * Error Register
212 register ERROR {
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H A Daic7xxx.reg2 * Aic7xxx register and scratch ram definitions.
55 register SCSISEQ {
69 * SCSI Transfer Control 0 Register (pp. 3-13).
72 register SXFRCTL0 {
85 * SCSI Transfer Control 1 Register (pp. 3-14,15).
88 register SXFRCTL1 {
101 * SCSI Control Signal Read Register (p. 3-15).
104 register SCSISIGI {
130 * SCSI Control Signal Write Register (p. 3-16).
131 * Writing to this register modifies the control signals on the bus. Only
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/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DRegisterFile.h10 /// This file defines a register mapping file class. This class is responsible
11 /// for managing hardware register files and the tracking of data dependencies
33 /// A reference to a register write.
35 /// This class is mainly used by the register file to describe register
36 /// mappings. It correlates a register write to the source index of the
68 /// Returns true if this register write has been executed, and the new
69 /// register value is therefore available to users.
81 /// Manages hardware register files, and tracks register definitions for
82 /// register renaming purposes.
86 // class RegisterMappingTracker is a physical register file (PRF) descriptor.
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/freebsd/sys/arm64/coresight/
H A Dcoresight_tmc.h34 #define TMC_RSZ 0x004 /* RAM Size Register */
35 #define TMC_STS 0x00C /* Status Register */
42 #define TMC_RRD 0x010 /* RAM Read Data Register */
43 #define TMC_RRP 0x014 /* RAM Read Pointer Register */
44 #define TMC_RWP 0x018 /* RAM Write Pointer Register */
45 #define TMC_TRG 0x01C /* Trigger Counter Register */
46 #define TMC_CTL 0x020 /* Control Register */
48 #define TMC_RWD 0x024 /* RAM Write Data Register */
49 #define TMC_MODE 0x028 /* Mode Register */
56 #define TMC_RRPHI 0x038 /* RAM Read Pointer High Register */
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H A Dcoresight_etm4x.h35 #define TRCPRGCTLR 0x004 /* Trace Programming Control Register */
37 #define TRCPROCSELR 0x008 /* Trace PE Select Control Register */
38 #define TRCSTATR 0x00C /* Trace Trace Status Register */
41 #define TRCCONFIGR 0x010 /* Trace Trace Configuration Register */
66 #define TRCAUXCTLR 0x018 /* Trace Auxiliary Control Register */
67 #define TRCEVENTCTL0R 0x020 /* Trace Event Control 0 Register */
68 #define TRCEVENTCTL1R 0x024 /* Trace Event Control 1 Register */
69 #define TRCSTALLCTLR 0x02C /* Trace Stall Control Register */
70 #define TRCTSCTLR 0x030 /* Trace Global Timestamp Control Register */
71 #define TRCSYNCPR 0x034 /* Trace Synchronization Period Register */
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/freebsd/sys/dev/ic/
H A Dcd180.h35 #define CD180_GIVR 0x40 /* Global Interrupt Verctor Register */
36 #define CD180_GICR 0x41 /* Global Interrupting Channel Register */
37 #define CD180_PILR1 0x61 /* Priority Interrupt Level Register 1 */
38 #define CD180_PILR2 0x62 /* Priority Interrupt Level Register 2 */
39 #define CD180_PILR3 0x63 /* Priority Interrupt Level Register 3 */
40 #define CD180_CAR 0x64 /* Channel Access Register */
41 #define CD180_GFRCR 0x6B /* Global Firmware Revision Code Register */
42 #define CD180_PPRH 0x70 /* Prescaler Period Register MSB */
43 #define CD180_PPRL 0x71 /* Prescaler Period Register LSB */
44 #define CD180_RDR 0x78 /* Receiver Data Register */
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h20 #include "llvm/CodeGen/Register.h"
92 /// Try to constrain Reg to the specified register class. If this fails,
93 /// create a new virtual register in the correct class.
95 /// \return The virtual register constrained to the right register class.
96 LLVM_ABI Register constrainRegToClass(MachineRegisterInfo &MRI,
98 const RegisterBankInfo &RBI, Register Reg,
101 /// Constrain the Register operand OpIdx, so that it is now constrained to the
103 /// If this fails, create a new virtual register in the correct class and insert
105 /// In both cases, the function also updates the register of RegMo. The debug
108 /// \return The virtual register constrained to the right register class.
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterCoalescer.h1 //===- RegisterCoalescer.h - Register Coalescing Interface ------*- C++ -*-===//
9 // This file contains the abstract interface for register coalescers,
10 // allowing them to interact with and query register allocators.
18 #include "llvm/CodeGen/Register.h"
26 /// A helper class for register coalescers. When deciding if
32 /// The register that will be left after coalescing. It can be a
33 /// virtual or physical register.
34 Register DstReg;
36 /// The virtual register that will be coalesced into dstReg.
37 Register SrcReg;
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/freebsd/sys/dev/sound/pci/
H A Denvy24.h63 #define PCIR_SCFG 0x60 /* System Configuration Register */
74 #define PCIR_ACL 0x61 /* AC-Link Configuration Register */
79 #define PCIR_I2S 0x62 /* I2S Converters Features Register */
89 #define PCIR_SPDIF 0x63 /* S/PDIF Configuration Register */
98 #define ENVY24_CCS_CTL 0x00 /* Control/Status Register */
106 #define ENVY24_CCS_IMASK 0x01 /* Interrupt Mask Register */
116 #define ENVY24_CCS_ISTAT 0x02 /* Interrupt Status Register */
126 #define ENVY24_CCS_INDEX 0x03 /* Envy24 Index Register */
127 #define ENVY24_CCS_DATA 0x04 /* Envy24 Data Register */
129 #define ENVY24_CCS_NMI1 0x05 /* NMI Status Register 1 */
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/freebsd/contrib/llvm-project/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_syscall_linux_loongarch64.inc14 // About local register variables:
15 // https://gcc.gnu.org/onlinedocs/gcc/Local-Register-Variables.html#Local-Register-Variables
31 register u64 a7 asm("$a7") = nr;
32 register u64 a0 asm("$a0");
42 register u64 a7 asm("$a7") = nr;
43 register u64 a0 asm("$a0") = arg1;
53 register u64 a7 asm("$a7") = nr;
54 register u64 a0 asm("$a0") = arg1;
55 register u64 a1 asm("$a1") = arg2;
66 register u64 a7 asm("$a7") = nr;
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H A Dsanitizer_syscall_linux_riscv64.inc13 // About local register variables:
14 // https://gcc.gnu.org/onlinedocs/gcc/Local-Register-Variables.html#Local-Register-Variables
34 register u64 a7 asm("a7") = nr;
35 register u64 a0 asm("a0");
45 register u64 a7 asm("a7") = nr;
46 register u64 a0 asm("a0") = arg1;
56 register u64 a7 asm("a7") = nr;
57 register u64 a0 asm("a0") = arg1;
58 register u64 a1 asm("a1") = arg2;
69 register u64 a7 asm("a7") = nr;
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/freebsd/share/man/man9/
H A Dmicroseq.953 .Sh PPBUS register model
56 Thus, any register described later has the same semantic than its counterpart
66 .Ss Data register
67 In compatible or nibble mode, writing to this register will drive data to the
70 setting the direction bit (PCD) in the control register.
71 Reads to this register
73 .Ss Device status register
74 This read-only register reflects the inputs on the parallel port interface.
86 .Ss Device control register
87 This register directly controls several output signals as well as enabling
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.h1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
10 // target register and register class definitions.
48 /// Used to encode a step in a register lane mask transformation.
63 /// CodeGenSubRegIndex - Represents a sub-register index.
84 // indexes are not used to create new register classes.
115 // register tuples) don't have a bit range, so it's OK to let in addComposite()
171 /// CodeGenRegister - Represents a register definition.
182 // Map SubRegIndex -> Register.
204 // Add this as a super-register to all sub-registers after the sub-register
217 // Return the sub-register index naming Reg as a sub-register of this
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/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h1 //===- MC/MCRegisterInfo.h - Target Register Description --------*- C++ -*-===//
10 // target machines register file. This information is used for a variety of
11 // purposed, especially register allocation.
52 /// getID() - Return the register class ID number.
65 /// getRegister - Return the specified register in the class.
68 assert(i < getNumRegs() && "Register number out of range!"); in getRegister()
72 /// contains - Return true if the specified register is included in this
73 /// register class. This does not include virtual registers.
88 /// Return the size of the physical register in bits if we are able to
95 /// this class. A negative number means the register class is very expensive
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/freebsd/sys/arm64/vmm/
H A Darm64.h43 Encode the index of a given register within VNCR into the enum value.
67 CSSELR_EL1, /* Cache Size Selection Register */
68 MDCCINT_EL1, /* Monitor DCC Interrupt Enable Register */
69 PAR_EL1, /* Physical Address Register */
72 PMCR_EL0, /* Performance Monitors Control Register */
100 HOST_CPTR_EL2, /* Architectural Feature Trap Register */
101 HOST_HCR_EL2, /* Hypervisor Configuration Register */
102 HOST_HCRX_EL2, /* Extended Hypervisor Configuration Register */
103 HOST_MDCR_EL2, /* Monitor Debug Configuration Register */
104 HOST_VPIDR_EL2, /* Virtualization Processor ID Register */
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