10b57cec5SDimitry Andric //===- RegisterCoalescer.h - Register Coalescing Interface ------*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This file contains the abstract interface for register coalescers, 100b57cec5SDimitry Andric // allowing them to interact with and query register allocators. 110b57cec5SDimitry Andric // 120b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric #ifndef LLVM_LIB_CODEGEN_REGISTERCOALESCER_H 150b57cec5SDimitry Andric #define LLVM_LIB_CODEGEN_REGISTERCOALESCER_H 160b57cec5SDimitry Andric 17*e8d8bef9SDimitry Andric #include "llvm/CodeGen/Register.h" 18*e8d8bef9SDimitry Andric 190b57cec5SDimitry Andric namespace llvm { 200b57cec5SDimitry Andric 210b57cec5SDimitry Andric class MachineInstr; 220b57cec5SDimitry Andric class TargetRegisterClass; 230b57cec5SDimitry Andric class TargetRegisterInfo; 240b57cec5SDimitry Andric 250b57cec5SDimitry Andric /// A helper class for register coalescers. When deciding if 260b57cec5SDimitry Andric /// two registers can be coalesced, CoalescerPair can determine if a copy 270b57cec5SDimitry Andric /// instruction would become an identity copy after coalescing. 280b57cec5SDimitry Andric class CoalescerPair { 290b57cec5SDimitry Andric const TargetRegisterInfo &TRI; 300b57cec5SDimitry Andric 310b57cec5SDimitry Andric /// The register that will be left after coalescing. It can be a 320b57cec5SDimitry Andric /// virtual or physical register. 33*e8d8bef9SDimitry Andric Register DstReg; 340b57cec5SDimitry Andric 350b57cec5SDimitry Andric /// The virtual register that will be coalesced into dstReg. 36*e8d8bef9SDimitry Andric Register SrcReg; 370b57cec5SDimitry Andric 380b57cec5SDimitry Andric /// The sub-register index of the old DstReg in the new coalesced register. 390b57cec5SDimitry Andric unsigned DstIdx = 0; 400b57cec5SDimitry Andric 410b57cec5SDimitry Andric /// The sub-register index of the old SrcReg in the new coalesced register. 420b57cec5SDimitry Andric unsigned SrcIdx = 0; 430b57cec5SDimitry Andric 440b57cec5SDimitry Andric /// True when the original copy was a partial subregister copy. 450b57cec5SDimitry Andric bool Partial = false; 460b57cec5SDimitry Andric 470b57cec5SDimitry Andric /// True when both regs are virtual and newRC is constrained. 480b57cec5SDimitry Andric bool CrossClass = false; 490b57cec5SDimitry Andric 500b57cec5SDimitry Andric /// True when DstReg and SrcReg are reversed from the original 510b57cec5SDimitry Andric /// copy instruction. 520b57cec5SDimitry Andric bool Flipped = false; 530b57cec5SDimitry Andric 540b57cec5SDimitry Andric /// The register class of the coalesced register, or NULL if DstReg 550b57cec5SDimitry Andric /// is a physreg. This register class may be a super-register of both 560b57cec5SDimitry Andric /// SrcReg and DstReg. 570b57cec5SDimitry Andric const TargetRegisterClass *NewRC = nullptr; 580b57cec5SDimitry Andric 590b57cec5SDimitry Andric public: CoalescerPair(const TargetRegisterInfo & tri)600b57cec5SDimitry Andric CoalescerPair(const TargetRegisterInfo &tri) : TRI(tri) {} 610b57cec5SDimitry Andric 620b57cec5SDimitry Andric /// Create a CoalescerPair representing a virtreg-to-physreg copy. 630b57cec5SDimitry Andric /// No need to call setRegisters(). CoalescerPair(Register VirtReg,MCRegister PhysReg,const TargetRegisterInfo & tri)64*e8d8bef9SDimitry Andric CoalescerPair(Register VirtReg, MCRegister PhysReg, 650b57cec5SDimitry Andric const TargetRegisterInfo &tri) 660b57cec5SDimitry Andric : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg) {} 670b57cec5SDimitry Andric 680b57cec5SDimitry Andric /// Set registers to match the copy instruction MI. Return 690b57cec5SDimitry Andric /// false if MI is not a coalescable copy instruction. 700b57cec5SDimitry Andric bool setRegisters(const MachineInstr*); 710b57cec5SDimitry Andric 720b57cec5SDimitry Andric /// Swap SrcReg and DstReg. Return false if swapping is impossible 730b57cec5SDimitry Andric /// because DstReg is a physical register, or SubIdx is set. 740b57cec5SDimitry Andric bool flip(); 750b57cec5SDimitry Andric 760b57cec5SDimitry Andric /// Return true if MI is a copy instruction that will become 770b57cec5SDimitry Andric /// an identity copy after coalescing. 780b57cec5SDimitry Andric bool isCoalescable(const MachineInstr*) const; 790b57cec5SDimitry Andric 800b57cec5SDimitry Andric /// Return true if DstReg is a physical register. isPhys()810b57cec5SDimitry Andric bool isPhys() const { return !NewRC; } 820b57cec5SDimitry Andric 830b57cec5SDimitry Andric /// Return true if the original copy instruction did not copy 840b57cec5SDimitry Andric /// the full register, but was a subreg operation. isPartial()850b57cec5SDimitry Andric bool isPartial() const { return Partial; } 860b57cec5SDimitry Andric 870b57cec5SDimitry Andric /// Return true if DstReg is virtual and NewRC is a smaller 880b57cec5SDimitry Andric /// register class than DstReg's. isCrossClass()890b57cec5SDimitry Andric bool isCrossClass() const { return CrossClass; } 900b57cec5SDimitry Andric 910b57cec5SDimitry Andric /// Return true when getSrcReg is the register being defined by 920b57cec5SDimitry Andric /// the original copy instruction. isFlipped()930b57cec5SDimitry Andric bool isFlipped() const { return Flipped; } 940b57cec5SDimitry Andric 950b57cec5SDimitry Andric /// Return the register (virtual or physical) that will remain 960b57cec5SDimitry Andric /// after coalescing. getDstReg()97*e8d8bef9SDimitry Andric Register getDstReg() const { return DstReg; } 980b57cec5SDimitry Andric 990b57cec5SDimitry Andric /// Return the virtual register that will be coalesced away. getSrcReg()100*e8d8bef9SDimitry Andric Register getSrcReg() const { return SrcReg; } 1010b57cec5SDimitry Andric 1020b57cec5SDimitry Andric /// Return the subregister index that DstReg will be coalesced into, or 0. getDstIdx()1030b57cec5SDimitry Andric unsigned getDstIdx() const { return DstIdx; } 1040b57cec5SDimitry Andric 1050b57cec5SDimitry Andric /// Return the subregister index that SrcReg will be coalesced into, or 0. getSrcIdx()1060b57cec5SDimitry Andric unsigned getSrcIdx() const { return SrcIdx; } 1070b57cec5SDimitry Andric 1080b57cec5SDimitry Andric /// Return the register class of the coalesced register. getNewRC()1090b57cec5SDimitry Andric const TargetRegisterClass *getNewRC() const { return NewRC; } 1100b57cec5SDimitry Andric }; 1110b57cec5SDimitry Andric 1120b57cec5SDimitry Andric } // end namespace llvm 1130b57cec5SDimitry Andric 1140b57cec5SDimitry Andric #endif // LLVM_LIB_CODEGEN_REGISTERCOALESCER_H 115