Lines Matching full:register
29 #define TSEC_REG_ID 0x000 /* Controller ID register #1. */
30 #define TSEC_REG_ID2 0x004 /* Controller ID register #2. */
33 #define TSEC_REG_IEVENT 0x010 /* Interrupt event register */
34 #define TSEC_REG_IMASK 0x014 /* Interrupt mask register */
35 #define TSEC_REG_EDIS 0x018 /* Error disabled register */
36 #define TSEC_REG_ECNTRL 0x020 /* Ethernet control register */
37 #define TSEC_REG_MINFLR 0x024 /* Minimum frame length register */
38 #define TSEC_REG_PTV 0x028 /* Pause time value register */
39 #define TSEC_REG_DMACTRL 0x02c /* DMA control register */
40 #define TSEC_REG_TBIPA 0x030 /* TBI PHY address register */
43 #define TSEC_REG_FIFO_PAUSE_CTRL 0x04c /* FIFO pause control register */
44 #define TSEC_REG_FIFO_TX_THR 0x08c /* FIFO transmit threshold register */
45 #define TSEC_REG_FIFO_TX_STARVE 0x098 /* FIFO transmit starve register */
47 * register */
50 #define TSEC_REG_TCTRL 0x100 /* Transmit control register */
51 #define TSEC_REG_TSTAT 0x104 /* Transmit Status Register */
52 #define TSEC_REG_TBDLEN 0x10c /* TxBD data length register */
54 * configuration register */
55 #define TSEC_REG_CTBPTR 0x124 /* Current TxBD pointer register */
56 #define TSEC_REG_TBPTR 0x184 /* TxBD pointer register */
57 #define TSEC_REG_TBASE 0x204 /* TxBD base address register */
58 #define TSEC_REG_OSTBD 0x2b0 /* Out-of-sequence TxBD register */
60 * register */
63 #define TSEC_REG_RCTRL 0x300 /* Receive control register */
64 #define TSEC_REG_RSTAT 0x304 /* Receive status register */
65 #define TSEC_REG_RBDLEN 0x30c /* RxBD data length register */
67 * configuration register */
68 #define TSEC_REG_CRBPTR 0x324 /* Current RxBD pointer register */
69 #define TSEC_REG_MRBLR 0x340 /* Maximum receive buffer length register */
70 #define TSEC_REG_RBPTR 0x384 /* RxBD pointer register */
71 #define TSEC_REG_RBASE 0x404 /* RxBD base address register */
74 #define TSEC_REG_MACCFG1 0x500 /* MAC configuration 1 register */
75 #define TSEC_REG_MACCFG2 0x504 /* MAC configuration 2 register */
77 * register */
78 #define TSEC_REG_HAFDUP 0x50c /* Half-duplex register */
79 #define TSEC_REG_MAXFRM 0x510 /* Maximum frame length register */
81 #define TSEC_REG_MIIMCFG 0x0 /* MII Management configuration register */
82 #define TSEC_REG_MIIMCOM 0x4 /* MII Management command register */
83 #define TSEC_REG_MIIMADD 0x8 /* MII Management address register */
84 #define TSEC_REG_MIIMCON 0xc /* MII Management control register */
85 #define TSEC_REG_MIIMSTAT 0x10 /* MII Management status register */
86 #define TSEC_REG_MIIMIND 0x14 /* MII Management indicator register */
87 #define TSEC_REG_IFSTAT 0x53c /* Interface status register */
88 #define TSEC_REG_MACSTNADDR1 0x540 /* Station address register, part 1 */
89 #define TSEC_REG_MACSTNADDR2 0x544 /* Station address register, part 2 */
93 * frame counter register */
95 * frame counter register */
97 * frame counter register */
99 * frame counter register */
101 * frame counter register */
103 * frame counter register */
105 * good VLAN frame counter register */
108 #define TSEC_REG_MON_RBYT 0x69c /* Receive byte counter register */
109 #define TSEC_REG_MON_RPKT 0x6a0 /* Receive packet counter register */
110 #define TSEC_REG_MON_RFCS 0x6a4 /* Receive FCS error counter register */
112 * register */
114 * register */
116 * register */
118 * register */
120 * register */
122 * register */
124 * register */
125 #define TSEC_REG_MON_RCDE 0x6c4 /* Receive code error counter register */
127 * register */
129 * register */
131 * register */
132 #define TSEC_REG_MON_RFRG 0x6d4 /* Receive fragments counter register */
133 #define TSEC_REG_MON_RJBR 0x6d8 /* Receive jabber counter register */
134 #define TSEC_REG_MON_RDRP 0x6dc /* Receive drop counter register */
137 #define TSEC_REG_MON_TBYT 0x6e0 /* Transmit byte counter register */
138 #define TSEC_REG_MON_TPKT 0x6e4 /* Transmit packet counter register */
140 * register */
142 * register */
144 * register */
146 * register */
148 * counter register */
150 * register */
152 * register */
154 * register */
156 * counter register */
158 * register */
159 #define TSEC_REG_MON_TDRP 0x714 /* Transmit drop frame counter register */
160 #define TSEC_REG_MON_TJBR 0x718 /* Transmit jabber frame counter register */
161 #define TSEC_REG_MON_TFCS 0x71c /* Transmit FCS error counter register */
162 #define TSEC_REG_MON_TXCF 0x720 /* Transmit control frame counter register */
164 * register */
166 * register */
168 * register */
171 #define TSEC_REG_MON_CAR1 0x730 /* Carry register one register */
172 #define TSEC_REG_MON_CAR2 0x734 /* Carry register two register */
173 #define TSEC_REG_MON_CAM1 0x738 /* Carry register one mask register */
174 #define TSEC_REG_MON_CAM2 0x73c /* Carry register two mask register */
177 #define TSEC_REG_IADDR0 0x800 /* Indivdual address register 0 */
178 #define TSEC_REG_IADDR1 0x804 /* Indivdual address register 1 */
179 #define TSEC_REG_IADDR2 0x808 /* Indivdual address register 2 */
180 #define TSEC_REG_IADDR3 0x80c /* Indivdual address register 3 */
181 #define TSEC_REG_IADDR4 0x810 /* Indivdual address register 4 */
182 #define TSEC_REG_IADDR5 0x814 /* Indivdual address register 5 */
183 #define TSEC_REG_IADDR6 0x818 /* Indivdual address register 6 */
184 #define TSEC_REG_IADDR7 0x81c /* Indivdual address register 7 */
185 #define TSEC_REG_GADDR0 0x880 /* Group address register 0 */
186 #define TSEC_REG_GADDR1 0x884 /* Group address register 1 */
187 #define TSEC_REG_GADDR2 0x888 /* Group address register 2 */
188 #define TSEC_REG_GADDR3 0x88c /* Group address register 3 */
189 #define TSEC_REG_GADDR4 0x890 /* Group address register 4 */
190 #define TSEC_REG_GADDR5 0x894 /* Group address register 5 */
191 #define TSEC_REG_GADDR6 0x898 /* Group address register 6 */
192 #define TSEC_REG_GADDR7 0x89c /* Group address register 7 */
197 #define TSEC_REG_ATTR 0xbf8 /* Attributes Register */
198 #define TSEC_REG_ATTRELI 0xbfc /* Attributes EL & EI register */
239 #define TSEC_IEVENT_MSRO 0x04000000 /* MSTAT Register Overflow */
260 #define TSEC_IMASK_MSROEN 0x04000000 /* MSTAT register overflow interrupt */