Lines Matching full:register
1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
10 // target register and register class definitions.
49 /// Used to encode a step in a register lane mask transformation.
64 /// CodeGenSubRegIndex - Represents a sub-register index.
85 // indexes are not used to create new register classes.
116 // register tuples) don't have a bit range, so it's OK to let in addComposite()
172 /// CodeGenRegister - Represents a register definition.
183 // Map SubRegIndex -> Register.
202 // Add this as a super-register to all sub-registers after the sub-register
215 // Return the sub-register index naming Reg as a sub-register of this
216 // register. Returns NULL if Reg is not a sub-register.
233 // register in 'Aliases'.
238 // Get the topological signature of this register. This is a small integer
240 // identical sub-register structure. That is, they support the same set of
241 // sub-register indices mapping to the same kind of sub-registers
248 // List of register units in ascending order.
255 // Get the list of register units.
263 // Get the native register units. This is a prefix of getRegUnits().
270 // Inherit register units from subregisters.
274 // Adopt a register unit for pressure tracking.
278 // Get the sum of this register's register unit weights.
296 // Super-registers where this is the first explicit sub-register.
331 // registers have a SubRegIndex sub-register.
335 // Map SubRegIndex -> set of super-reg classes. This is all register
363 /// A register class is artificial if all its members are artificial.
365 /// Generate register pressure set for this register class and any class
388 // Return true if this class contains the register.
393 // instruction operand where a register of this classis required. It must
405 // registers have a SubIdx sub-register.
418 /// SubClass is a class where every register has SubIdx and SubRegClass is a
419 /// class where every register is covered by the SubIdx subregister of
430 // getSuperRegClasses - Returns a bit vector of all register classes
464 // Get a bit vector of TopoSigs present in this register class.
467 // Get a weight of this register class.
470 // Populate a unique sorted list of units from a register set.
477 // A key representing the parts of a register class used for forming
494 // Create a non-user defined register class.
500 // Get ordering value among register base classes.
508 // Register categories are used when we need to deterine the category a
509 // register falls into (GPR, vector, fixed, etc.) without having to know
528 // Register units are used to model interference and register pressure.
529 // Every register is assigned one or more register units such that two
530 // registers overlap if and only if they have a register unit in common.
532 // Normally, one register unit is created per leaf register. Non-leaf
535 // Weight assigned to this RegUnit for estimating register pressure.
536 // This is useful when equalizing weights in register classes with mixed
537 // register topologies.
548 // A register unit is artificial if at least one of its roots is
602 // Includes native (0..NumNativeRegUnits-1) and adopted register units.
605 // Register classes.
611 // Register categories.
618 // Remember each unique set of register units. Initially, this contains a
619 // unique set for each register class. Simliar sets are coalesced with
626 // NOTE: This could grow beyond the number of register classes when we map
627 // register units to lists of unit sets. If the list of unit sets does not
628 // already exist for a register class, we create a new entry in this vector.
631 // Give each register unit set an order based on sorting criteria.
645 // Infer missing register classes.
661 // Compute a weight for each register unit created during getSubRegs.
667 // Populate the Composite map from sub-register relationships.
670 // Compute a lane mask for each sub-register index.
673 /// Computes a lane mask for each register unit enumerated by a physical
674 /// register.
685 // Sub-register indices. The first NumNamedIndices are defined by the user
699 // Find or create a sub-register index representing the A+B composition.
703 // Find or create a sub-register index representing the concatenation of
715 // Find a register from its Record def.
718 // Get a Register's index into the Registers array.
734 // Create a native register unit that is associated with one or two root
746 // Create a new non-native register unit that can be adopted by a register
754 // Native units are the singular unit of a leaf register. Register aliasing
756 // register additional weight but don't affect aliasing.
778 // Find a register class from its def.
781 /// getRegisterClassForRegister - Find the register class that contains the
782 /// specified physical register. If the register is not in a register
783 /// class, return null. If the register is in multiple classes, and the
790 // the physical register. If \p VT is specified, it will only find classes
816 // Get the number of register pressure dimensions.
819 // Get a set of register unit IDs for a given dimension of pressure.
825 // register classes if some register units appeared in a list of sets that
826 // did not correspond to an existing register class.
831 // Get a list of pressure set IDs for a register class. Liveness of a
832 // register in this class impacts each pressure set in this list by the
833 // weight of the register. An exact solution requires all registers in a
839 // Computed derived records such as missing sub-register indices.
843 // The returned BitVector will have a bit set for each register in Regs,
851 // Bit mask of lanes that cover their registers. A sub-register index whose
853 // another sub-register with the same or larger lane mask.