| /linux/Documentation/netlink/specs/ |
| H A D | dpll.yaml | 1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
2 ---
8 -
16 -
20 -
23 render-max: true
24 -
26 name: lock-status
31 -
34 dpll was not yet locked to any valid input (or forced by setting
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-driver-zynqmp-fpga | 1 What: /sys/bus/platform/drivers/zynqmp_fpga_manager/firmware:zynqmp-firmware:pcap/status
9 https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration
18 BIT(2) 0: MMCMs/PLLs are not locked
19 1: MMCMs/PLLs are locked
24 BIT(4) 0: Start-up sequence has not finished
25 1: Start-up sequence has finished
27 BIT(5) 0: All I/Os are placed in High-Z state
30 BIT(6) 0: Flip-flops and block RAM are write disabled
31 1: Flip-flops and block RAM are write enabled
54 BIT(17) System Monitor over-temperature if set
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| H A D | sysfs-bus-iio-frequency-ad9523 | 8 Contact: linux-iio@vger.kernel.org
18 Contact: linux-iio@vger.kernel.org
21 pllY is locked.
25 Contact: linux-iio@vger.kernel.org
29 with their predefined phase offsets (out_altvoltageY_phase).
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| /linux/drivers/iio/frequency/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 # Phase-Locked Loop (PLL) frequency synthesizers
27 # Phase-Locked Loop (PLL) frequency synthesizers
30 menu "Phase-Locked Loop (PLL) frequency synthesizers"
100 Downconverter with integrated Fractional-N PLL and VCO.
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| /linux/Documentation/devicetree/bindings/dpll/ |
| H A D | dpll-device.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dpll/dpll-device.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Digital Phase-Locked Loop (DPLL) Device
10 - Ivan Vecera <ivecera@redhat.com>
13 Digital Phase-Locked Loop (DPLL) device is used for precise clock
16 output pins. Each DPLL channel can either produce pulse-per-clock signal
18 indicated by dpll-types property.
24 "#address-cells":
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| H A D | dpll-pin.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dpll/dpll-pin.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ivan Vecera <ivecera@redhat.com>
14 by a DPLL( Digital Phase-Locked Loop) device. The pin is identified by
26 connection-type:
31 esync-control:
39 supported-frequencies-hz:
43 - reg
|
| /linux/include/linux/ |
| H A D | ww_mutex.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
35 #define ww_mutex_base_is_locked(b) rt_mutex_base_is_locked(&(b)->rtmutex)
69 * @first_lock_dep_map: fake lockdep_map for first locked ww_mutex.
71 * lockdep requires the lockdep_map for the first locked ww_mutex
74 * fake locked ww_mutex lockdep map between ww_acquire_init() and
98 * ww_mutex_init - initialize the w/w mutex
106 * It is not allowed to initialize an already locked mutex.
111 ww_mutex_base_init(&lock->base, ww_class->mutex_name, &ww_class->mutex_key); in ww_mutex_init()
112 lock->ctx = NULL; in ww_mutex_init()
114 lock->ww_class = ww_class; in ww_mutex_init()
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| /linux/drivers/media/dvb-frontends/ |
| H A D | tda8261.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
29 const struct tda8261_config *config = state->config; in tda8261_read()
31 struct i2c_msg msg = { .addr = config->addr, .flags = I2C_M_RD,.buf = buf, .len = 1 }; in tda8261_read()
33 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) in tda8261_read()
41 const struct tda8261_config *config = state->config; in tda8261_write()
43 struct i2c_msg msg = { .addr = config->addr, .flags = 0, .buf = buf, .len = 4 }; in tda8261_write()
45 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) in tda8261_write()
53 struct tda8261_state *state = fe->tuner_priv; in tda8261_get_status()
64 pr_debug("%s: Tuner Phase Locked\n", __func__); in tda8261_get_status()
76 struct tda8261_state *state = fe->tuner_priv; in tda8261_get_frequency()
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| H A D | tda665x.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
27 const struct tda665x_config *config = state->config; in tda665x_read()
29 struct i2c_msg msg = { .addr = config->addr, .flags = I2C_M_RD, .buf = buf, .len = 2 }; in tda665x_read()
31 err = i2c_transfer(state->i2c, &msg, 1); in tda665x_read()
43 const struct tda665x_config *config = state->config; in tda665x_write()
45 struct i2c_msg msg = { .addr = config->addr, .flags = 0, .buf = buf, .len = length }; in tda665x_write()
47 err = i2c_transfer(state->i2c, &msg, 1); in tda665x_write()
59 struct tda665x_state *state = fe->tuner_priv; in tda665x_get_frequency()
61 *frequency = state->frequency; in tda665x_get_frequency()
68 struct tda665x_state *state = fe->tuner_priv; in tda665x_get_status()
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| H A D | dib3000mb_priv.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
17 { pr_err("while sending 0x%04x to 0x%04x.", val, reg); return -EREMOTEIO; }
159 * Dual Automatic-Gain-Control
160 * - gains RF in tuner (AGC1)
161 * - gains IF after filtering (AGC2)
173 /* phase noise */
255 /* phase noise compensation inhibition */
297 * data diversity when having more than one chip on-board
313 /* time frame for Bit-Error-Rate calculation */
320 /* 142 - 152 FIFO parameters
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| /linux/Documentation/driver-api/ |
| H A D | dpll.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 PLL - Phase Locked Loop is an electronic circuit which syntonizes clock
14 DPLL - Digital Phase Locked Loop is an integrated circuit which in
15 addition to plain PLL behavior incorporates a digital phase detector
82 - ``DPLL_PIN_STATE_CONNECTED`` - the pin is used to drive dpll device
83 - ``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not used to drive dpll
89 - ``DPLL_PIN_STATE_SELECTABLE`` - the pin shall be considered as valid
91 - ``DPLL_PIN_STATE_DISCONNECTED`` - the pin shall be not considered as
104 1) Set on a pin - the configuration affects all dpll devices pin is
106 2) Set on a pin-dpll tuple - the configuration affects only selected
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| /linux/Documentation/devicetree/bindings/clock/ti/ |
| H A D | apll.txt | 4 register-mapped APLL with usually two selectable input clocks
5 (reference clock and bypass clock), with analog phase locked
8 modes (locked, low power stop etc.) APLL mostly behaves like
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
16 - #clock-cells : from common clock binding; shall be set to 0.
17 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
18 - reg : address and length of the register set for controlling the APLL.
20 "control" - contains the control register offset
21 "idlest" - contains the idlest register offset
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| H A D | dpll.txt | 4 register-mapped DPLL with usually two selectable input clocks
5 (reference clock and bypass clock), with digital phase locked
8 modes (locked, low power stop etc.) This binding has several
9 sub-types, which effectively result in slightly different setup
12 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible : shall be one of:
16 "ti,omap3-dpll-clock",
17 "ti,omap3-dpll-core-clock",
18 "ti,omap3-dpll-per-clock",
19 "ti,omap3-dpll-per-j-type-clock",
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| /linux/drivers/dpll/zl3073x/ |
| H A D | dpll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
28 * struct zl3073x_dpll_pin - DPLL pin
39 * @phase_offset: last saved pin phase offset
65 * zl3073x_dpll_is_input_pin - check if the pin is input one
73 return pin->dir == DPLL_PIN_DIRECTION_INPUT; in zl3073x_dpll_is_input_pin()
77 * zl3073x_dpll_is_p_pin - check if the pin is P-pin
80 * Return: true if the pin is P-pin, false if it is N-pin
85 return zl3073x_is_p_pin(pin->id); in zl3073x_dpll_is_p_pin()
96 *direction = pin->dir; in zl3073x_dpll_pin_direction_get()
102 * zl3073x_dpll_input_ref_frequency_get - get input reference frequency
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| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | hisilicon,hi3798cv200-dw-mshc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/hisilicon,hi3798cv200-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yang Xiwen <forbidden405@outlook.com>
15 - hisilicon,hi3798cv200-dw-mshc
16 - hisilicon,hi3798mv200-dw-mshc
26 - description: bus interface unit clock
27 - description: card interface unit clock
28 - description: card input sample phase clock
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| /linux/include/uapi/linux/ |
| H A D | dpll.h | 1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
2 /* Do not edit directly, auto-generated from: */
4 /* YNL-GEN uapi header */
13 * enum dpll_mode - working modes a dpll can support, differentiates if and how
25 DPLL_MODE_MAX = (__DPLL_MODE_MAX - 1)
29 * enum dpll_lock_status - provides information of dpll device lock status,
31 * @DPLL_LOCK_STATUS_UNLOCKED: dpll was not yet locked to any valid input (or
33 * @DPLL_LOCK_STATUS_LOCKED: dpll is locked to a valid signal, but no holdover
35 * @DPLL_LOCK_STATUS_LOCKED_HO_ACQ: dpll is locked and holdover acquired
36 * @DPLL_LOCK_STATUS_HOLDOVER: dpll is in holdover state - lost a valid lock or
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| H A D | pps.h | 1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
5 * Copyright (C) 2005-2009 Rodolfo Giometti <giometti@linux.it>
43 /* 32-bit vs. 64-bit compatibility.
120 use a phase-locked loop */
122 use a frequency-locked loop */
124 * Here begins the implementation-specific part!
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| /linux/sound/soc/tegra/ |
| H A D | tegra20_spdif.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * tegra20_spdif.h - Definitions for Tegra20 SPDIF driver
6 * Copyright (C) 2011 - NVIDIA, Inc.
9 * Copyright (c) 2008-2009, NVIDIA Corporation
125 * This bit is asserted when the receiver first locked onto the
169 /* B-preamble detection status: 0=not detected, 1=B-preamble detected */
210 * bi-phase period.
215 /* Data strobe mode: 0=Auto-locked 1=Manual locked */
219 * Manual data strobe time within the bi-phase clock period (in terms of
220 * the number of over-sampling clocks).
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| /linux/drivers/clk/qcom/ |
| H A D | clk-pll.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
10 #include "clk-regmap.h"
13 * struct pll_freq_tbl - PLL frequency table
28 * struct clk_pll - phase locked loop (PLL)
37 * @hw: handle between common and hardware-specific interfaces
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| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | fsl,imx8qm-lvds-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
15 groups of four data lanes of LVDS data streams. A phase-locked
30 - fsl,imx8qm-lvds-phy
31 - mixel,28fdsoi-lvds-1250-8ch-tx-pll
33 "#phy-cells":
42 power-domains:
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| /linux/Documentation/driver-api/nvdimm/ |
| H A D | security.rst | 6 ---------------
16 ------------------
22 that DIMM. The following states are available: disabled, unlocked, locked,
28 update <old_keyid> <new_keyid> - enable or update passphrase.
29 disable <keyid> - disable enabled security and remove key.
30 freeze - freeze changing of security states.
31 erase <keyid> - delete existing user encryption key.
32 overwrite <keyid> - wipe the entire nvdimm.
33 master_update <keyid> <new_keyid> - enable or update master passphrase.
34 master_erase <keyid> - delete existing user encryption key.
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| /linux/Documentation/gpu/nova/core/ |
| H A D | devinit.rst | 1 .. SPDX-License-Identifier: GPL-2.0
6 The devinit process is complex and subject to change. This document provides a high-level
18 nova-core driver is even loaded. On an Ampere GPU, the devinit ucode is separate from the
19 FWSEC ucode. It is launched by FWSEC, which runs on the GSP in 'heavy-secure' mode, while
20 devinit runs on the PMU in 'light-secure' mode.
23 ------------------------
28 3. Clock and PLL (Phase-Locked Loop) configuration
31 Low-level Firmware Initialization Flow
32 --------------------------------------
37 These low-level GPU firmware components are typically:
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| /linux/include/drm/ |
| H A D | task_barrier.h | 27 * Reusable 2 PHASE task barrier (rendez-vous point) implementation for N tasks.
28 * Based on the Little book of semaphores - https://greenteapress.com/wp/semaphores/
57 tb->n = 0; in task_barrier_init()
58 atomic_set(&tb->count, 0); in task_barrier_init()
59 sema_init(&tb->enter_turnstile, 0); in task_barrier_init()
60 sema_init(&tb->exit_turnstile, 0); in task_barrier_init()
65 tb->n++; in task_barrier_add_task()
70 tb->n--; in task_barrier_rem_task()
76 * When all thread passed this code the entry barrier is back to locked state.
80 if (atomic_inc_return(&tb->count) == tb->n) in task_barrier_enter()
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| /linux/arch/sparc/include/asm/ |
| H A D | spitfire.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define TSB_EXTENSION_P 0x0000000000000048 /* Ultra-III and later */
25 #define TSB_EXTENSION_S 0x0000000000000050 /* Ultra-III and later, D-TLB only */
26 #define TSB_EXTENSION_N 0x0000000000000058 /* Ultra-III and later */
27 #define TLB_TAG_ACCESS_EXT 0x0000000000000060 /* Ultra-III+ and later */
38 #define SPITFIRE_HIGHEST_LOCKED_TLBENT (64 - 1)
39 #define CHEETAH_HIGHEST_LOCKED_TLBENT (16 - 1)
58 * to identify the CPU type in the setup phase
201 /* Cheetah has "all non-locked" tlb flushes. */
218 /* Cheetah has a 4-tlb layout so direct access is a bit different.
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| /linux/drivers/scsi/aic7xxx/ |
| H A D | aic79xx.reg | 4 * Copyright (c) 1994-2001, 2004 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
19 * 3. Neither the names of the above-listed copyright holders nor the names
62 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
69 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
76 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { \
136 BAD_PHASE, /* unknown scsi bus phase */
142 * Returned to data phase
187 * A command with a non-zero
839 * PCI-X Control
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