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/linux/Documentation/ABI/testing/
H A Dsysfs-driver-zynqmp-fpga1 What: /sys/bus/platform/drivers/zynqmp_fpga_manager/firmware:zynqmp-firmware:pcap/status
9 https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration
18 BIT(2) 0: MMCMs/PLLs are not locked
19 1: MMCMs/PLLs are locked
24 BIT(4) 0: Start-up sequence has not finished
25 1: Start-up sequence has finished
27 BIT(5) 0: All I/Os are placed in High-Z state
30 BIT(6) 0: Flip-flops and block RAM are write disabled
31 1: Flip-flops and block RAM are write enabled
54 BIT(17) System Monitor over-temperature if set
[all …]
H A Dsysfs-bus-iio-frequency-ad95238 Contact: linux-iio@vger.kernel.org
18 Contact: linux-iio@vger.kernel.org
21 pllY is locked.
25 Contact: linux-iio@vger.kernel.org
29 with their predefined phase offsets (out_altvoltageY_phase).
/linux/drivers/iio/frequency/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 # Phase-Locked Loop (PLL) frequency synthesizers
27 # Phase-Locked Loop (PLL) frequency synthesizers
30 menu "Phase-Locked Loop (PLL) frequency synthesizers"
100 Downconverter with integrated Fractional-N PLL and VCO.
/linux/Documentation/devicetree/bindings/dpll/
H A Ddpll-device.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dpll/dpll-device.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Digital Phase-Locked Loop (DPLL) Device
10 - Ivan Vecera <ivecera@redhat.com>
13 Digital Phase-Locked Loop (DPLL) device is used for precise clock
16 output pins. Each DPLL channel can either produce pulse-per-clock signal
18 indicated by dpll-types property.
24 "#address-cells":
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/linux/drivers/media/dvb-frontends/
H A Dtda8261.c1 // SPDX-License-Identifier: GPL-2.0-or-later
29 const struct tda8261_config *config = state->config; in tda8261_read()
31 struct i2c_msg msg = { .addr = config->addr, .flags = I2C_M_RD,.buf = buf, .len = 1 }; in tda8261_read()
33 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) in tda8261_read()
41 const struct tda8261_config *config = state->config; in tda8261_write()
43 struct i2c_msg msg = { .addr = config->addr, .flags = 0, .buf = buf, .len = 4 }; in tda8261_write()
45 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) in tda8261_write()
53 struct tda8261_state *state = fe->tuner_priv; in tda8261_get_status()
64 pr_debug("%s: Tuner Phase Locked\n", __func__); in tda8261_get_status()
76 struct tda8261_state *state = fe->tuner_priv; in tda8261_get_frequency()
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H A Dtda665x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
27 const struct tda665x_config *config = state->config; in tda665x_read()
29 struct i2c_msg msg = { .addr = config->addr, .flags = I2C_M_RD, .buf = buf, .len = 2 }; in tda665x_read()
31 err = i2c_transfer(state->i2c, &msg, 1); in tda665x_read()
43 const struct tda665x_config *config = state->config; in tda665x_write()
45 struct i2c_msg msg = { .addr = config->addr, .flags = 0, .buf = buf, .len = length }; in tda665x_write()
47 err = i2c_transfer(state->i2c, &msg, 1); in tda665x_write()
59 struct tda665x_state *state = fe->tuner_priv; in tda665x_get_frequency()
61 *frequency = state->frequency; in tda665x_get_frequency()
68 struct tda665x_state *state = fe->tuner_priv; in tda665x_get_status()
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H A Ddib3000mb_priv.h1 /* SPDX-License-Identifier: GPL-2.0-only */
17 { pr_err("while sending 0x%04x to 0x%04x.", val, reg); return -EREMOTEIO; }
159 * Dual Automatic-Gain-Control
160 * - gains RF in tuner (AGC1)
161 * - gains IF after filtering (AGC2)
173 /* phase noise */
255 /* phase noise compensation inhibition */
297 * data diversity when having more than one chip on-board
313 /* time frame for Bit-Error-Rate calculation */
320 /* 142 - 152 FIFO parameters
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/linux/Documentation/devicetree/bindings/clock/ti/
H A Dapll.txt4 register-mapped APLL with usually two selectable input clocks
5 (reference clock and bypass clock), with analog phase locked
8 modes (locked, low power stop etc.) APLL mostly behaves like
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
16 - #clock-cells : from common clock binding; shall be set to 0.
17 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
18 - reg : address and length of the register set for controlling the APLL.
20 "control" - contains the control register offset
21 "idlest" - contains the idlest register offset
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H A Ddpll.txt4 register-mapped DPLL with usually two selectable input clocks
5 (reference clock and bypass clock), with digital phase locked
8 modes (locked, low power stop etc.) This binding has several
9 sub-types, which effectively result in slightly different setup
12 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible : shall be one of:
16 "ti,omap3-dpll-clock",
17 "ti,omap3-dpll-core-clock",
18 "ti,omap3-dpll-per-clock",
19 "ti,omap3-dpll-per-j-type-clock",
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/linux/Documentation/devicetree/bindings/mmc/
H A Dhisilicon,hi3798cv200-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/hisilicon,hi3798cv200-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yang Xiwen <forbidden405@outlook.com>
15 - hisilicon,hi3798cv200-dw-mshc
16 - hisilicon,hi3798mv200-dw-mshc
26 - description: bus interface unit clock
27 - description: card interface unit clock
28 - description: card input sample phase clock
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/linux/drivers/dpll/zl3073x/
H A Ddpll.c1 // SPDX-License-Identifier: GPL-2.0-only
29 * struct zl3073x_dpll_pin - DPLL pin
40 * @phase_gran: phase adjustment granularity
42 * @phase_offset: last saved pin phase offset
72 * zl3073x_dpll_is_input_pin - check if the pin is input one
80 return pin->dir == DPLL_PIN_DIRECTION_INPUT; in zl3073x_dpll_is_input_pin()
84 * zl3073x_dpll_is_p_pin - check if the pin is P-pin
87 * Return: true if the pin is P-pin, false if it is N-pin
92 return zl3073x_is_p_pin(pin->id); in zl3073x_dpll_is_p_pin()
103 *direction = pin->dir; in zl3073x_dpll_pin_direction_get()
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/linux/sound/soc/tegra/
H A Dtegra20_spdif.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * tegra20_spdif.h - Definitions for Tegra20 SPDIF driver
6 * Copyright (C) 2011 - NVIDIA, Inc.
9 * Copyright (c) 2008-2009, NVIDIA Corporation
125 * This bit is asserted when the receiver first locked onto the
169 /* B-preamble detection status: 0=not detected, 1=B-preambl
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/linux/drivers/clk/qcom/
H A Dclk-pll.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
10 #include "clk-regmap.h"
13 * struct pll_freq_tbl - PLL frequency table
28 * struct clk_pll - phase locked loop (PLL)
37 * @hw: handle between common and hardware-specific interfaces
/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8qm-lvds-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
15 groups of four data lanes of LVDS data streams. A phase-locked
30 - fsl,imx8qm-lvds-phy
31 - mixel,28fdsoi-lvds-1250-8ch-tx-pll
33 "#phy-cells":
42 power-domains:
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/linux/include/uapi/linux/
H A Dpps.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
5 * Copyright (C) 2005-2009 Rodolfo Giometti <giometti@linux.it>
43 /* 32-bit vs. 64-bit compatibility.
120 use a phase-locked loop */
122 use a frequency-locked loop */
124 * Here begins the implementation-specific part!
/linux/Documentation/driver-api/nvdimm/
H A Dsecurity.rst6 ---------------
16 ------------------
22 that DIMM. The following states are available: disabled, unlocked, locked,
28 update <old_keyid> <new_keyid> - enable or update passphrase.
29 disable <keyid> - disable enabled security and remove key.
30 freeze - freeze changing of security states.
31 erase <keyid> - delete existing user encryption key.
32 overwrite <keyid> - wipe the entire nvdimm.
33 master_update <keyid> <new_keyid> - enable or update master passphrase.
34 master_erase <keyid> - delete existing user encryption key.
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/linux/Documentation/gpu/nova/core/
H A Ddevinit.rst1 .. SPDX-License-Identifier: GPL-2.0
6 The devinit process is complex and subject to change. This document provides a high-level
18 nova-core driver is even loaded. On an Ampere GPU, the devinit ucode is separate from the
19 FWSEC ucode. It is launched by FWSEC, which runs on the GSP in 'heavy-secure' mode, while
20 devinit runs on the PMU in 'light-secure' mode.
23 ------------------------
28 3. Clock and PLL (Phase-Locked Loop) configuration
31 Low-level Firmware Initialization Flow
32 --------------------------------------
37 These low-level GPU firmware components are typically:
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/linux/include/drm/
H A Dtask_barrier.h27 * Reusable 2 PHASE task barrier (rendez-vous point) implementation for N tasks.
28 * Based on the Little book of semaphores - https://greenteapress.com/wp/semaphores/
57 tb->n = 0; in task_barrier_init()
58 atomic_set(&tb->count, 0); in task_barrier_init()
59 sema_init(&tb->enter_turnstile, 0); in task_barrier_init()
60 sema_init(&tb->exit_turnstile, 0); in task_barrier_init()
65 tb->n++; in task_barrier_add_task()
70 tb->n--; in task_barrier_rem_task()
76 * When all thread passed this code the entry barrier is back to locked state.
80 if (atomic_inc_return(&tb->count) == tb->n) in task_barrier_enter()
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/linux/drivers/scsi/aic7xxx/
H A Daic79xx.reg4 * Copyright (c) 1994-2001, 2004 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
19 * 3. Neither the names of the above-listed copyright holders nor the names
62 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
69 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
76 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { \
136 BAD_PHASE, /* unknown scsi bus phase */
142 * Returned to data phase
187 * A command with a non-zero
839 * PCI-X Control
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/linux/drivers/input/keyboard/
H A Dmaple_keyb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Porting to 2.6 Copyright (c) Adrian McMenamin, 2007 - 2009
83 struct input_dev *dev = kbd->dev; in dc_scan_kbd()
90 keycode = kbd->keycode[code]; in dc_scan_kbd()
92 input_report_key(dev, keycode, (kbd->new[0] >> i) & 1); in dc_scan_kbd()
96 ptr = memchr(kbd->new + 2, kbd->old[i], 6); in dc_scan_kbd()
97 code = kbd->old[i]; in dc_scan_kbd()
99 keycode = kbd->keycode[code]; in dc_scan_kbd()
104 dev_dbg(&dev->dev, in dc_scan_kbd()
108 ptr = memchr(kbd->old + 2, kbd->new[i], 6); in dc_scan_kbd()
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/linux/sound/usb/
H A Dendpoint.c1 // SPDX-License-Identifier: GPL-2.0-or-later
42 atomic_t locked; member
99 if (u->urb && u->buffer_size) in release_urb_ctx()
100 usb_free_coherent(u->ep->chip->dev, u->buffer_size, in release_urb_ctx()
101 u->urb->transfer_buffer, in release_urb_ctx()
102 u->urb->transfer_dma); in release_urb_ctx()
103 usb_free_urb(u->urb); in release_urb_ctx()
104 u->urb = NULL; in release_urb_ctx()
105 u->buffer_size = 0; in release_urb_ctx()
111 case -ENODEV: in usb_error_string()
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/linux/drivers/scsi/pcmcia/
H A Dsym53c500_cs.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * A rewrite of the pcmcia-cs add-on driver for newer (circa 1997)
8 * The pcmcia-cs add-on version of this driver is not supported
188 * Repository for per-instance host data.
198 int phase; member
201 enum Phase { enum
284 reqlen -= len & 0xfc; in SYM53C500_pio_read()
286 while (len--) { in SYM53C500_pio_read()
288 reqlen--; in SYM53C500_pio_read()
335 reqlen -= len & 0xfc; in SYM53C500_pio_write()
[all …]
/linux/drivers/iio/dac/
H A Dadi-axi-dac.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright 2016-2024 Analog Devices Inc.
8 #include <linux/adi-axi-common.h>
28 #include <linux/iio/buffer-dmaengine.h>
32 #include "ad3552r-hs.h"
126 guard(mutex)(&st->lock); in axi_dac_enable()
127 ret = regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG, in axi_dac_enable()
132 * Make sure the DRP (Dynamic Reconfiguration Port) is locked. Not all in axi_dac_enable()
136 ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_DRP_STATUS_REG, in axi_dac_enable()
143 return regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG, in axi_dac_enable()
[all …]
/linux/drivers/md/persistent-data/
H A Ddm-transaction-manager.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include "dm-block-manager.h"
16 /*----------------------------------------------------------------*/
20 * of the on-disk data structures by limiting access to writeable blocks.
28 * The non-blocking version of a transaction manager is intended for use in
30 * You create the non-blocking variant from a normal tm. The interface is
31 * the same, except that most functions will just return -EWOULDBLOCK.
40 * We use a 2-phase commit here.
59 * dm_tm_new_block() is pretty self-explanatory. Make sure you do actually
74 * confuse this with a clone - you shouldn't access the orig block after
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/linux/Documentation/devicetree/bindings/clock/
H A Dfsl,qoriq-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 multiple phase locked loops (PLL) to create a variety of frequencies
24 --------------- -------------
36 - items:
37 - enum:
38 - fsl,p2041-clockgen
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