Lines Matching +full:phase +full:- +full:locked

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dpll/dpll-device.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Digital Phase-Locked Loop (DPLL) Device
10   - Ivan Vecera <ivecera@redhat.com>
13   Digital Phase-Locked Loop (DPLL) device is used for precise clock
16   output pins. Each DPLL channel can either produce pulse-per-clock signal
18   indicated by dpll-types property.
24   "#address-cells":
27   "#size-cells":
30   dpll-types:
32     $ref: /schemas/types.yaml#/definitions/non-unique-string-array
36   input-pins:
42       "#address-cells":
44       "#size-cells":
48       "^pin@[0-9a-f]+$":
49         $ref: /schemas/dpll/dpll-pin.yaml
53       - "#address-cells"
54       - "#size-cells"
56   output-pins:
62       "#address-cells":
64       "#size-cells":
68       "^pin@[0-9]+$":
69         $ref: /schemas/dpll/dpll-pin.yaml
73       - "#address-cells"
74       - "#size-cells"