1*0afcee10SIvan Vecera# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*0afcee10SIvan Vecera%YAML 1.2 3*0afcee10SIvan Vecera--- 4*0afcee10SIvan Vecera$id: http://devicetree.org/schemas/dpll/dpll-device.yaml# 5*0afcee10SIvan Vecera$schema: http://devicetree.org/meta-schemas/core.yaml# 6*0afcee10SIvan Vecera 7*0afcee10SIvan Veceratitle: Digital Phase-Locked Loop (DPLL) Device 8*0afcee10SIvan Vecera 9*0afcee10SIvan Veceramaintainers: 10*0afcee10SIvan Vecera - Ivan Vecera <ivecera@redhat.com> 11*0afcee10SIvan Vecera 12*0afcee10SIvan Veceradescription: 13*0afcee10SIvan Vecera Digital Phase-Locked Loop (DPLL) device is used for precise clock 14*0afcee10SIvan Vecera synchronization in networking and telecom hardware. The device can 15*0afcee10SIvan Vecera have one or more channels (DPLLs) and one or more physical input and 16*0afcee10SIvan Vecera output pins. Each DPLL channel can either produce pulse-per-clock signal 17*0afcee10SIvan Vecera or drive ethernet equipment clock. The type of each channel can be 18*0afcee10SIvan Vecera indicated by dpll-types property. 19*0afcee10SIvan Vecera 20*0afcee10SIvan Veceraproperties: 21*0afcee10SIvan Vecera $nodename: 22*0afcee10SIvan Vecera pattern: "^dpll(@.*)?$" 23*0afcee10SIvan Vecera 24*0afcee10SIvan Vecera "#address-cells": 25*0afcee10SIvan Vecera const: 0 26*0afcee10SIvan Vecera 27*0afcee10SIvan Vecera "#size-cells": 28*0afcee10SIvan Vecera const: 0 29*0afcee10SIvan Vecera 30*0afcee10SIvan Vecera dpll-types: 31*0afcee10SIvan Vecera description: List of DPLL channel types, one per DPLL instance. 32*0afcee10SIvan Vecera $ref: /schemas/types.yaml#/definitions/non-unique-string-array 33*0afcee10SIvan Vecera items: 34*0afcee10SIvan Vecera enum: [pps, eec] 35*0afcee10SIvan Vecera 36*0afcee10SIvan Vecera input-pins: 37*0afcee10SIvan Vecera type: object 38*0afcee10SIvan Vecera description: DPLL input pins 39*0afcee10SIvan Vecera unevaluatedProperties: false 40*0afcee10SIvan Vecera 41*0afcee10SIvan Vecera properties: 42*0afcee10SIvan Vecera "#address-cells": 43*0afcee10SIvan Vecera const: 1 44*0afcee10SIvan Vecera "#size-cells": 45*0afcee10SIvan Vecera const: 0 46*0afcee10SIvan Vecera 47*0afcee10SIvan Vecera patternProperties: 48*0afcee10SIvan Vecera "^pin@[0-9a-f]+$": 49*0afcee10SIvan Vecera $ref: /schemas/dpll/dpll-pin.yaml 50*0afcee10SIvan Vecera unevaluatedProperties: false 51*0afcee10SIvan Vecera 52*0afcee10SIvan Vecera required: 53*0afcee10SIvan Vecera - "#address-cells" 54*0afcee10SIvan Vecera - "#size-cells" 55*0afcee10SIvan Vecera 56*0afcee10SIvan Vecera output-pins: 57*0afcee10SIvan Vecera type: object 58*0afcee10SIvan Vecera description: DPLL output pins 59*0afcee10SIvan Vecera unevaluatedProperties: false 60*0afcee10SIvan Vecera 61*0afcee10SIvan Vecera properties: 62*0afcee10SIvan Vecera "#address-cells": 63*0afcee10SIvan Vecera const: 1 64*0afcee10SIvan Vecera "#size-cells": 65*0afcee10SIvan Vecera const: 0 66*0afcee10SIvan Vecera 67*0afcee10SIvan Vecera patternProperties: 68*0afcee10SIvan Vecera "^pin@[0-9]+$": 69*0afcee10SIvan Vecera $ref: /schemas/dpll/dpll-pin.yaml 70*0afcee10SIvan Vecera unevaluatedProperties: false 71*0afcee10SIvan Vecera 72*0afcee10SIvan Vecera required: 73*0afcee10SIvan Vecera - "#address-cells" 74*0afcee10SIvan Vecera - "#size-cells" 75*0afcee10SIvan Vecera 76*0afcee10SIvan VeceraadditionalProperties: true 77