13badff3aSVadim Fedorenko /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */ 23badff3aSVadim Fedorenko /* Do not edit directly, auto-generated from: */ 33badff3aSVadim Fedorenko /* Documentation/netlink/specs/dpll.yaml */ 43badff3aSVadim Fedorenko /* YNL-GEN uapi header */ 53badff3aSVadim Fedorenko 63badff3aSVadim Fedorenko #ifndef _UAPI_LINUX_DPLL_H 73badff3aSVadim Fedorenko #define _UAPI_LINUX_DPLL_H 83badff3aSVadim Fedorenko 93badff3aSVadim Fedorenko #define DPLL_FAMILY_NAME "dpll" 103badff3aSVadim Fedorenko #define DPLL_FAMILY_VERSION 1 113badff3aSVadim Fedorenko 123badff3aSVadim Fedorenko /** 133badff3aSVadim Fedorenko * enum dpll_mode - working modes a dpll can support, differentiates if and how 143badff3aSVadim Fedorenko * dpll selects one of its inputs to syntonize with it, valid values for 153badff3aSVadim Fedorenko * DPLL_A_MODE attribute 163badff3aSVadim Fedorenko * @DPLL_MODE_MANUAL: input can be only selected by sending a request to dpll 173badff3aSVadim Fedorenko * @DPLL_MODE_AUTOMATIC: highest prio input pin auto selected by dpll 183badff3aSVadim Fedorenko */ 193badff3aSVadim Fedorenko enum dpll_mode { 203badff3aSVadim Fedorenko DPLL_MODE_MANUAL = 1, 213badff3aSVadim Fedorenko DPLL_MODE_AUTOMATIC, 223badff3aSVadim Fedorenko 233badff3aSVadim Fedorenko /* private: */ 243badff3aSVadim Fedorenko __DPLL_MODE_MAX, 253badff3aSVadim Fedorenko DPLL_MODE_MAX = (__DPLL_MODE_MAX - 1) 263badff3aSVadim Fedorenko }; 273badff3aSVadim Fedorenko 283badff3aSVadim Fedorenko /** 293badff3aSVadim Fedorenko * enum dpll_lock_status - provides information of dpll device lock status, 303badff3aSVadim Fedorenko * valid values for DPLL_A_LOCK_STATUS attribute 313badff3aSVadim Fedorenko * @DPLL_LOCK_STATUS_UNLOCKED: dpll was not yet locked to any valid input (or 323badff3aSVadim Fedorenko * forced by setting DPLL_A_MODE to DPLL_MODE_DETACHED) 333badff3aSVadim Fedorenko * @DPLL_LOCK_STATUS_LOCKED: dpll is locked to a valid signal, but no holdover 343badff3aSVadim Fedorenko * available 353badff3aSVadim Fedorenko * @DPLL_LOCK_STATUS_LOCKED_HO_ACQ: dpll is locked and holdover acquired 363badff3aSVadim Fedorenko * @DPLL_LOCK_STATUS_HOLDOVER: dpll is in holdover state - lost a valid lock or 373badff3aSVadim Fedorenko * was forced by disconnecting all the pins (latter possible only when dpll 383badff3aSVadim Fedorenko * lock-state was already DPLL_LOCK_STATUS_LOCKED_HO_ACQ, if dpll lock-state 393badff3aSVadim Fedorenko * was not DPLL_LOCK_STATUS_LOCKED_HO_ACQ, the dpll's lock-state shall remain 403badff3aSVadim Fedorenko * DPLL_LOCK_STATUS_UNLOCKED) 413badff3aSVadim Fedorenko */ 423badff3aSVadim Fedorenko enum dpll_lock_status { 433badff3aSVadim Fedorenko DPLL_LOCK_STATUS_UNLOCKED = 1, 443badff3aSVadim Fedorenko DPLL_LOCK_STATUS_LOCKED, 453badff3aSVadim Fedorenko DPLL_LOCK_STATUS_LOCKED_HO_ACQ, 463badff3aSVadim Fedorenko DPLL_LOCK_STATUS_HOLDOVER, 473badff3aSVadim Fedorenko 483badff3aSVadim Fedorenko /* private: */ 493badff3aSVadim Fedorenko __DPLL_LOCK_STATUS_MAX, 503badff3aSVadim Fedorenko DPLL_LOCK_STATUS_MAX = (__DPLL_LOCK_STATUS_MAX - 1) 513badff3aSVadim Fedorenko }; 523badff3aSVadim Fedorenko 53*cf4f0f1eSJiri Pirko /** 54*cf4f0f1eSJiri Pirko * enum dpll_lock_status_error - if previous status change was done due to a 55*cf4f0f1eSJiri Pirko * failure, this provides information of dpll device lock status error. Valid 56*cf4f0f1eSJiri Pirko * values for DPLL_A_LOCK_STATUS_ERROR attribute 57*cf4f0f1eSJiri Pirko * @DPLL_LOCK_STATUS_ERROR_NONE: dpll device lock status was changed without 58*cf4f0f1eSJiri Pirko * any error 59*cf4f0f1eSJiri Pirko * @DPLL_LOCK_STATUS_ERROR_UNDEFINED: dpll device lock status was changed due 60*cf4f0f1eSJiri Pirko * to undefined error. Driver fills this value up in case it is not able to 61*cf4f0f1eSJiri Pirko * obtain suitable exact error type. 62*cf4f0f1eSJiri Pirko * @DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN: dpll device lock status was changed 63*cf4f0f1eSJiri Pirko * because of associated media got down. This may happen for example if dpll 64*cf4f0f1eSJiri Pirko * device was previously locked on an input pin of type 65*cf4f0f1eSJiri Pirko * PIN_TYPE_SYNCE_ETH_PORT. 66*cf4f0f1eSJiri Pirko * @DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH: the FFO 67*cf4f0f1eSJiri Pirko * (Fractional Frequency Offset) between the RX and TX symbol rate on the 68*cf4f0f1eSJiri Pirko * media got too high. This may happen for example if dpll device was 69*cf4f0f1eSJiri Pirko * previously locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT. 70*cf4f0f1eSJiri Pirko */ 71*cf4f0f1eSJiri Pirko enum dpll_lock_status_error { 72*cf4f0f1eSJiri Pirko DPLL_LOCK_STATUS_ERROR_NONE = 1, 73*cf4f0f1eSJiri Pirko DPLL_LOCK_STATUS_ERROR_UNDEFINED, 74*cf4f0f1eSJiri Pirko DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN, 75*cf4f0f1eSJiri Pirko DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH, 76*cf4f0f1eSJiri Pirko 77*cf4f0f1eSJiri Pirko /* private: */ 78*cf4f0f1eSJiri Pirko __DPLL_LOCK_STATUS_ERROR_MAX, 79*cf4f0f1eSJiri Pirko DPLL_LOCK_STATUS_ERROR_MAX = (__DPLL_LOCK_STATUS_ERROR_MAX - 1) 80*cf4f0f1eSJiri Pirko }; 81*cf4f0f1eSJiri Pirko 823badff3aSVadim Fedorenko #define DPLL_TEMP_DIVIDER 1000 833badff3aSVadim Fedorenko 843badff3aSVadim Fedorenko /** 853badff3aSVadim Fedorenko * enum dpll_type - type of dpll, valid values for DPLL_A_TYPE attribute 863badff3aSVadim Fedorenko * @DPLL_TYPE_PPS: dpll produces Pulse-Per-Second signal 873badff3aSVadim Fedorenko * @DPLL_TYPE_EEC: dpll drives the Ethernet Equipment Clock 883badff3aSVadim Fedorenko */ 893badff3aSVadim Fedorenko enum dpll_type { 903badff3aSVadim Fedorenko DPLL_TYPE_PPS = 1, 913badff3aSVadim Fedorenko DPLL_TYPE_EEC, 923badff3aSVadim Fedorenko 933badff3aSVadim Fedorenko /* private: */ 943badff3aSVadim Fedorenko __DPLL_TYPE_MAX, 953badff3aSVadim Fedorenko DPLL_TYPE_MAX = (__DPLL_TYPE_MAX - 1) 963badff3aSVadim Fedorenko }; 973badff3aSVadim Fedorenko 983badff3aSVadim Fedorenko /** 993badff3aSVadim Fedorenko * enum dpll_pin_type - defines possible types of a pin, valid values for 1003badff3aSVadim Fedorenko * DPLL_A_PIN_TYPE attribute 1013badff3aSVadim Fedorenko * @DPLL_PIN_TYPE_MUX: aggregates another layer of selectable pins 1023badff3aSVadim Fedorenko * @DPLL_PIN_TYPE_EXT: external input 1033badff3aSVadim Fedorenko * @DPLL_PIN_TYPE_SYNCE_ETH_PORT: ethernet port PHY's recovered clock 1043badff3aSVadim Fedorenko * @DPLL_PIN_TYPE_INT_OSCILLATOR: device internal oscillator 1053badff3aSVadim Fedorenko * @DPLL_PIN_TYPE_GNSS: GNSS recovered clock 1063badff3aSVadim Fedorenko */ 1073badff3aSVadim Fedorenko enum dpll_pin_type { 1083badff3aSVadim Fedorenko DPLL_PIN_TYPE_MUX = 1, 1093badff3aSVadim Fedorenko DPLL_PIN_TYPE_EXT, 1103badff3aSVadim Fedorenko DPLL_PIN_TYPE_SYNCE_ETH_PORT, 1113badff3aSVadim Fedorenko DPLL_PIN_TYPE_INT_OSCILLATOR, 1123badff3aSVadim Fedorenko DPLL_PIN_TYPE_GNSS, 1133badff3aSVadim Fedorenko 1143badff3aSVadim Fedorenko /* private: */ 1153badff3aSVadim Fedorenko __DPLL_PIN_TYPE_MAX, 1163badff3aSVadim Fedorenko DPLL_PIN_TYPE_MAX = (__DPLL_PIN_TYPE_MAX - 1) 1173badff3aSVadim Fedorenko }; 1183badff3aSVadim Fedorenko 1193badff3aSVadim Fedorenko /** 1203badff3aSVadim Fedorenko * enum dpll_pin_direction - defines possible direction of a pin, valid values 1213badff3aSVadim Fedorenko * for DPLL_A_PIN_DIRECTION attribute 1223badff3aSVadim Fedorenko * @DPLL_PIN_DIRECTION_INPUT: pin used as a input of a signal 1233badff3aSVadim Fedorenko * @DPLL_PIN_DIRECTION_OUTPUT: pin used to output the signal 1243badff3aSVadim Fedorenko */ 1253badff3aSVadim Fedorenko enum dpll_pin_direction { 1263badff3aSVadim Fedorenko DPLL_PIN_DIRECTION_INPUT = 1, 1273badff3aSVadim Fedorenko DPLL_PIN_DIRECTION_OUTPUT, 1283badff3aSVadim Fedorenko 1293badff3aSVadim Fedorenko /* private: */ 1303badff3aSVadim Fedorenko __DPLL_PIN_DIRECTION_MAX, 1313badff3aSVadim Fedorenko DPLL_PIN_DIRECTION_MAX = (__DPLL_PIN_DIRECTION_MAX - 1) 1323badff3aSVadim Fedorenko }; 1333badff3aSVadim Fedorenko 1343badff3aSVadim Fedorenko #define DPLL_PIN_FREQUENCY_1_HZ 1 1353badff3aSVadim Fedorenko #define DPLL_PIN_FREQUENCY_10_KHZ 10000 1363badff3aSVadim Fedorenko #define DPLL_PIN_FREQUENCY_77_5_KHZ 77500 1373badff3aSVadim Fedorenko #define DPLL_PIN_FREQUENCY_10_MHZ 10000000 1383badff3aSVadim Fedorenko 1393badff3aSVadim Fedorenko /** 1403badff3aSVadim Fedorenko * enum dpll_pin_state - defines possible states of a pin, valid values for 1413badff3aSVadim Fedorenko * DPLL_A_PIN_STATE attribute 1423badff3aSVadim Fedorenko * @DPLL_PIN_STATE_CONNECTED: pin connected, active input of phase locked loop 1433badff3aSVadim Fedorenko * @DPLL_PIN_STATE_DISCONNECTED: pin disconnected, not considered as a valid 1443badff3aSVadim Fedorenko * input 1453badff3aSVadim Fedorenko * @DPLL_PIN_STATE_SELECTABLE: pin enabled for automatic input selection 1463badff3aSVadim Fedorenko */ 1473badff3aSVadim Fedorenko enum dpll_pin_state { 1483badff3aSVadim Fedorenko DPLL_PIN_STATE_CONNECTED = 1, 1493badff3aSVadim Fedorenko DPLL_PIN_STATE_DISCONNECTED, 1503badff3aSVadim Fedorenko DPLL_PIN_STATE_SELECTABLE, 1513badff3aSVadim Fedorenko 1523badff3aSVadim Fedorenko /* private: */ 1533badff3aSVadim Fedorenko __DPLL_PIN_STATE_MAX, 1543badff3aSVadim Fedorenko DPLL_PIN_STATE_MAX = (__DPLL_PIN_STATE_MAX - 1) 1553badff3aSVadim Fedorenko }; 1563badff3aSVadim Fedorenko 1573badff3aSVadim Fedorenko /** 1583badff3aSVadim Fedorenko * enum dpll_pin_capabilities - defines possible capabilities of a pin, valid 1593badff3aSVadim Fedorenko * flags on DPLL_A_PIN_CAPABILITIES attribute 1603badff3aSVadim Fedorenko * @DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE: pin direction can be changed 1613badff3aSVadim Fedorenko * @DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE: pin priority can be changed 1623badff3aSVadim Fedorenko * @DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE: pin state can be changed 1633badff3aSVadim Fedorenko */ 1643badff3aSVadim Fedorenko enum dpll_pin_capabilities { 1653badff3aSVadim Fedorenko DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE = 1, 1663badff3aSVadim Fedorenko DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE = 2, 1673badff3aSVadim Fedorenko DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE = 4, 1683badff3aSVadim Fedorenko }; 1693badff3aSVadim Fedorenko 170c3c6ab95SArkadiusz Kubalewski #define DPLL_PHASE_OFFSET_DIVIDER 1000 171c3c6ab95SArkadiusz Kubalewski 1723badff3aSVadim Fedorenko enum dpll_a { 1733badff3aSVadim Fedorenko DPLL_A_ID = 1, 1743badff3aSVadim Fedorenko DPLL_A_MODULE_NAME, 1753badff3aSVadim Fedorenko DPLL_A_PAD, 1763badff3aSVadim Fedorenko DPLL_A_CLOCK_ID, 1773badff3aSVadim Fedorenko DPLL_A_MODE, 1783badff3aSVadim Fedorenko DPLL_A_MODE_SUPPORTED, 1793badff3aSVadim Fedorenko DPLL_A_LOCK_STATUS, 1803badff3aSVadim Fedorenko DPLL_A_TEMP, 1813badff3aSVadim Fedorenko DPLL_A_TYPE, 182*cf4f0f1eSJiri Pirko DPLL_A_LOCK_STATUS_ERROR, 1833badff3aSVadim Fedorenko 1843badff3aSVadim Fedorenko __DPLL_A_MAX, 1853badff3aSVadim Fedorenko DPLL_A_MAX = (__DPLL_A_MAX - 1) 1863badff3aSVadim Fedorenko }; 1873badff3aSVadim Fedorenko 1883badff3aSVadim Fedorenko enum dpll_a_pin { 1893badff3aSVadim Fedorenko DPLL_A_PIN_ID = 1, 1903badff3aSVadim Fedorenko DPLL_A_PIN_PARENT_ID, 1913badff3aSVadim Fedorenko DPLL_A_PIN_MODULE_NAME, 1923badff3aSVadim Fedorenko DPLL_A_PIN_PAD, 1933badff3aSVadim Fedorenko DPLL_A_PIN_CLOCK_ID, 1943badff3aSVadim Fedorenko DPLL_A_PIN_BOARD_LABEL, 1953badff3aSVadim Fedorenko DPLL_A_PIN_PANEL_LABEL, 1963badff3aSVadim Fedorenko DPLL_A_PIN_PACKAGE_LABEL, 1973badff3aSVadim Fedorenko DPLL_A_PIN_TYPE, 1983badff3aSVadim Fedorenko DPLL_A_PIN_DIRECTION, 1993badff3aSVadim Fedorenko DPLL_A_PIN_FREQUENCY, 2003badff3aSVadim Fedorenko DPLL_A_PIN_FREQUENCY_SUPPORTED, 2013badff3aSVadim Fedorenko DPLL_A_PIN_FREQUENCY_MIN, 2023badff3aSVadim Fedorenko DPLL_A_PIN_FREQUENCY_MAX, 2033badff3aSVadim Fedorenko DPLL_A_PIN_PRIO, 2043badff3aSVadim Fedorenko DPLL_A_PIN_STATE, 2053badff3aSVadim Fedorenko DPLL_A_PIN_CAPABILITIES, 2063badff3aSVadim Fedorenko DPLL_A_PIN_PARENT_DEVICE, 2073badff3aSVadim Fedorenko DPLL_A_PIN_PARENT_PIN, 208c3c6ab95SArkadiusz Kubalewski DPLL_A_PIN_PHASE_ADJUST_MIN, 209c3c6ab95SArkadiusz Kubalewski DPLL_A_PIN_PHASE_ADJUST_MAX, 210c3c6ab95SArkadiusz Kubalewski DPLL_A_PIN_PHASE_ADJUST, 211c3c6ab95SArkadiusz Kubalewski DPLL_A_PIN_PHASE_OFFSET, 2128a6286c1SJiri Pirko DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET, 2133badff3aSVadim Fedorenko 2143badff3aSVadim Fedorenko __DPLL_A_PIN_MAX, 2153badff3aSVadim Fedorenko DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1) 2163badff3aSVadim Fedorenko }; 2173badff3aSVadim Fedorenko 2183badff3aSVadim Fedorenko enum dpll_cmd { 2193badff3aSVadim Fedorenko DPLL_CMD_DEVICE_ID_GET = 1, 2203badff3aSVadim Fedorenko DPLL_CMD_DEVICE_GET, 2213badff3aSVadim Fedorenko DPLL_CMD_DEVICE_SET, 2223badff3aSVadim Fedorenko DPLL_CMD_DEVICE_CREATE_NTF, 2233badff3aSVadim Fedorenko DPLL_CMD_DEVICE_DELETE_NTF, 2243badff3aSVadim Fedorenko DPLL_CMD_DEVICE_CHANGE_NTF, 2253badff3aSVadim Fedorenko DPLL_CMD_PIN_ID_GET, 2263badff3aSVadim Fedorenko DPLL_CMD_PIN_GET, 2273badff3aSVadim Fedorenko DPLL_CMD_PIN_SET, 2283badff3aSVadim Fedorenko DPLL_CMD_PIN_CREATE_NTF, 2293badff3aSVadim Fedorenko DPLL_CMD_PIN_DELETE_NTF, 2303badff3aSVadim Fedorenko DPLL_CMD_PIN_CHANGE_NTF, 2313badff3aSVadim Fedorenko 2323badff3aSVadim Fedorenko __DPLL_CMD_MAX, 2333badff3aSVadim Fedorenko DPLL_CMD_MAX = (__DPLL_CMD_MAX - 1) 2343badff3aSVadim Fedorenko }; 2353badff3aSVadim Fedorenko 2363badff3aSVadim Fedorenko #define DPLL_MCGRP_MONITOR "monitor" 2373badff3aSVadim Fedorenko 2383badff3aSVadim Fedorenko #endif /* _UAPI_LINUX_DPLL_H */ 239