1*4a902a02SLiu Ying# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4a902a02SLiu Ying%YAML 1.2 3*4a902a02SLiu Ying--- 4*4a902a02SLiu Ying$id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml# 5*4a902a02SLiu Ying$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4a902a02SLiu Ying 7*4a902a02SLiu Yingtitle: Mixel LVDS PHY for Freescale i.MX8qm SoC 8*4a902a02SLiu Ying 9*4a902a02SLiu Yingmaintainers: 10*4a902a02SLiu Ying - Liu Ying <victor.liu@nxp.com> 11*4a902a02SLiu Ying 12*4a902a02SLiu Yingdescription: | 13*4a902a02SLiu Ying The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC. 14*4a902a02SLiu Ying It converts two groups of four 7/10 bits of CMOS data into two 15*4a902a02SLiu Ying groups of four data lanes of LVDS data streams. A phase-locked 16*4a902a02SLiu Ying transmit clock is transmitted in parallel with each group of 17*4a902a02SLiu Ying data streams over a fifth LVDS link. Every cycle of the transmit 18*4a902a02SLiu Ying clock, 56/80 bits of input data are sampled and transmitted 19*4a902a02SLiu Ying through the two groups of LVDS data streams. Together with the 20*4a902a02SLiu Ying transmit clocks, the two groups of LVDS data streams form two 21*4a902a02SLiu Ying LVDS channels. 22*4a902a02SLiu Ying 23*4a902a02SLiu Ying The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled 24*4a902a02SLiu Ying by Control and Status Registers(CSR) module in the SoC. The CSR 25*4a902a02SLiu Ying module, as a system controller, contains the PHY's registers. 26*4a902a02SLiu Ying 27*4a902a02SLiu Yingproperties: 28*4a902a02SLiu Ying compatible: 29*4a902a02SLiu Ying enum: 30*4a902a02SLiu Ying - fsl,imx8qm-lvds-phy 31*4a902a02SLiu Ying - mixel,28fdsoi-lvds-1250-8ch-tx-pll 32*4a902a02SLiu Ying 33*4a902a02SLiu Ying "#phy-cells": 34*4a902a02SLiu Ying const: 1 35*4a902a02SLiu Ying description: | 36*4a902a02SLiu Ying Cell allows setting the LVDS channel index of the PHY. 37*4a902a02SLiu Ying Index 0 is for LVDS channel0 and index 1 is for LVDS channel1. 38*4a902a02SLiu Ying 39*4a902a02SLiu Ying clocks: 40*4a902a02SLiu Ying maxItems: 1 41*4a902a02SLiu Ying 42*4a902a02SLiu Ying power-domains: 43*4a902a02SLiu Ying maxItems: 1 44*4a902a02SLiu Ying 45*4a902a02SLiu Yingrequired: 46*4a902a02SLiu Ying - compatible 47*4a902a02SLiu Ying - "#phy-cells" 48*4a902a02SLiu Ying - clocks 49*4a902a02SLiu Ying - power-domains 50*4a902a02SLiu Ying 51*4a902a02SLiu YingadditionalProperties: false 52*4a902a02SLiu Ying 53*4a902a02SLiu Yingexamples: 54*4a902a02SLiu Ying - | 55*4a902a02SLiu Ying #include <dt-bindings/firmware/imx/rsrc.h> 56*4a902a02SLiu Ying phy { 57*4a902a02SLiu Ying compatible = "fsl,imx8qm-lvds-phy"; 58*4a902a02SLiu Ying #phy-cells = <1>; 59*4a902a02SLiu Ying clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>; 60*4a902a02SLiu Ying power-domains = <&pd IMX_SC_R_LVDS_0>; 61*4a902a02SLiu Ying }; 62