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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZPatterns.td1 //===-- SystemZPatterns.td - SystemZ-specific pattern rules ---*- tblgen-*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // Record that INSN performs a 64-bit version of unary operator OPERATOR
10 // in which the operand is sign-extended from 32 to 64 bits.
18 // Record that INSN performs a 64-bit version of binary operator OPERATOR
20 // is sign-extended from a 32-bit register.
38 // Record that INSN performs a binary read-modify-write operation,
68 // INSN stores the low 32 bits of a GPR to a memory with addressing mode MODE.
75 // INSN and INSNY are an RX/RXY pair of instructions that store the low
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H A DSystemZISelLowering.cpp1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
35 #define DEBUG_TYPE "systemz-lower"
47 // Chain if this is a strict floating-point comparison.
64 // Classify VT as either 32 or 64 bit.
65 static bool is32Bit(EVT VT) { in is32Bit() argument
66 switch (VT.getSimpleVT().SimpleTy) { in is32Bit()
127 setStackPointerRegisterToSaveRestore(Regs->getStackPointerRegister()); in SystemZTargetLowering()
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H A DSystemZISelLowering.h1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
43 // Wraps a TargetGlobalAddress that should be loaded using PC-relative
58 // Floating-point comparisons. The two operands are the values to compare.
69 // operand 1 is the 4-bit condition-code mask, with bit N in
70 // big-endian order meaning "branch if CC=N"; operand 2 is the
75 // mask of condition-code values for which operand 0 should be
81 // base of the dynamically-allocatable area.
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/freebsd/share/man/man4/
H A Dpci.435 .Bd -ragged -offset indent
40 .Pq SR-IOV :
41 .Bd -ragged -offset indent
45 To compile in support for native PCI-express HotPlug:
46 .Bd -ragged -offset indent
91 or a BAR read access could have function-specific side-effects.
113 driver also includes support for PCI-PCI bridges,
114 various platform-specific Host-PCI bridges,
126 .Bl -tag -width 012345678901234
147 .Bl -tag -width match_buf_len
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H A Dacpi_battery.439 An ACPI-compatible battery device supports either a Control
65 .Bl -tag -width indent
66 .It Dv ACPIIO_BATT_GET_UNITS Vt int
69 .It Dv ACPIIO_BATT_GET_BATTINFO Vt struct acpi_battinfo
71 .Bl -tag -width indent
78 .Bl -tag -width indent
84 Remaining battery life is critically low.
93 .Li -1
96 .It Dv ACPIIO_BATT_GET_BIX Vt struct acpi_bix
110 .Bl -tag -width indent
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
60 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
62 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
64 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
71 CALL_NOLINK, // Function call with branch not branch-and-link.
72 tSECALL, // CMSE non-secure function call.
76 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h1 //===- CodeGen/ValueTypes.h - Low-Level Target independ. types --*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the set of low-level target independent types which various
13 //===----------------------------------------------------------------------===//
44 bool operator==(EVT VT) const {
45 return !(*this != VT);
47 bool operator!=(EVT VT) const {
48 if (V.SimpleTy != VT.V.SimpleTy)
51 return LLVMTy != VT.LLVMTy;
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H A DTargetLowering.h1 //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
20 //===----------------------------------------------------------------------===//
105 ILP, // Scheduling for ILP in low register pressure mode.
128 bool MemcpyStrSrc; // Indicates whether the memcpy source is an in-register
193 /// This base class for TargetLowering contains the SelectionDAG-independent
215 TypeScalarizeVector, // Replace this one-element vector with its element.
224 // vector, this is non-trivial at SelectionDAG
230 /// in order to type-legalize it.
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H A DSelectionDAG.h1 //===- llvm/CodeGen/SelectionDAG.h - InstSelection DAG ----------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
114 SDVTListNode(const FoldingSetNodeIDRef ID, const EVT *VT, unsigned int Num) :
115 FastID(ID), VTs(VT), NumVTs(Num) {
179 /// it from the Node-to-DbgValues map.
199 return I->second;
216 /// This is used to represent a portion of an LLVM function in a low-level
222 /// The representation used by the SelectionDAG is a target-independent
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/freebsd/sys/x86/iommu/
H A Dintel_intrmap.c1 /*-
65 uint64_t low, uint16_t rid);
77 if (unit == NULL || !unit->ir_enabled) { in dmar_alloc_msi_intr()
79 cookies[i] = -1; in dmar_alloc_msi_intr()
83 error = vmem_alloc(unit->irtids, count, M_FIRSTFIT | M_NOWAIT, in dmar_alloc_msi_intr()
101 uint64_t low; in dmar_map_msi_intr() local
110 * See VT-d specification, 5.1.6 Remapping Hardware - in dmar_map_msi_intr()
121 if (unit == NULL || !unit->ir_enabled || cookie == -1) in dmar_map_msi_intr()
124 low = (DMAR_X2APIC(unit) ? DMAR_IRTE1_DST_x2APIC(cpu) : in dmar_map_msi_intr()
128 dmar_ir_program_irte(unit, cookie, low, rid); in dmar_map_msi_intr()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
15 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
18 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "legalize-types"
33 //===----------------------------------------------------------------------===//
35 //===----------------------------------------------------------------------===//
37 /// PromoteIntegerResult - This method is called when a result of a node is
42 LLVM_DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG)); in PromoteIntegerResult()
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H A DLegalizeVectorOps.cpp1 //===- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
22 // or operations that happen to take a vector which are custom-lowered;
27 //===----------------------------------------------------------------------===//
92 /// Implement expand-based legalization of vector operations.
94 /// This is just a high-level routine to dispatch to specific code paths for
111 /// Shuffles the low lanes of the operand into place and bitcasts to the proper
118 /// Shuffles the low lanes of the operand into place, bitcasts to the proper
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
62 /// #0 - The incoming token chain
63 /// #1 - The callee
64 /// #2 - The number of arg bytes the caller pushes on the stack.
65 /// #3 - The number of arg bytes the callee pops off the stack.
66 /// #4 - The value to pass in AL/AX/EAX (optional)
67 /// #5 - The value to pass in DL/DX/EDX (optional)
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H A DX86ISelLowering.cpp1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
71 #define DEBUG_TYPE "x86-isel"
74 "x86-experimental-pref-innermost-loop-alignment", cl::init(4),
78 "alignment set by x86-experimental-pref-loop-alignment."),
82 "x86-br-merging-base-cost", cl::init(2),
88 "will be merged, and above which conditionals will be split. Set to -1 "
93 "x86-br-merging-ccmp-bias", cl::init(6),
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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
42 #define DEBUG_TYPE "xcore-lower"
118 // Conversion of i64 -> double produces constantpool nodes in XCoreTargetLowering()
122 for (MVT VT : MVT::integer_valuetypes()) { in XCoreTargetLowering() local
123 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in XCoreTargetLowering()
124 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in XCoreTargetLowering()
125 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in XCoreTargetLowering()
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/freebsd/sys/arm/freescale/imx/
H A Dfiles.imx625 dev/hdmi/dwc_hdmi.c optional vt dwc_hdmi
26 arm/freescale/imx/imx6_hdmi.c optional vt imx6_hdmi
28 arm/freescale/imx/imx6_ipu.c optional vt imx6_ipu
45 # Low-level serial console for debugging early kernel startup.
50 sdma-imx6q.c optional fslsdma \
51 compile-with "${AWK} -f $S/tools/fw_stub.awk sdma-imx6q.bin:sdma-imx6q -msdma -c${.TARGET}" \
52 no-ctfconvert no-implicit-rule before-depend local \
53 clean "sdma-imx6q.c"
54 sdma-imx6q.fwo optional fslsdma \
55 dependency "sdma-imx6q.bin" \
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrSIMD.td1 // WebAssemblyInstrSIMD.td - WebAssembly SIMD codegen support -*- tablegen -*-//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// WebAssembly SIMD operand code-gen constructs.
12 //===----------------------------------------------------------------------===//
29 string asmstr_s = "", bits<32> simdop = -1,
37 string asmstr_s = "", bits<32> simdop = -1> {
44 string asmstr_s = "", bits<32> simdop = -1> {
62 // -2^(n-1) <= Imm < 2^n
63 "return -(1 << ("#SIZE#" - 1)) <= Imm && Imm < (1 << "#SIZE#");"
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/freebsd/share/man/man5/
H A Drc.conf.593 to store jail-specific configuration options.
120 .Bl -tag -width indent-two
122 .Pq Vt bool
131 .Pq Vt bool
139 .Pq Vt bool
146 .Pq Vt str
181 .Pq Vt bool
194 .Pq Vt str
198 .Pq Vt str
206 .Pq Vt int
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1 //===-- AArch64ISelDAGToDAG.cpp - A dag to dag inst selector for AArch64 --===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "aarch64-isel"
34 //===--------------------------------------------------------------------===//
35 /// AArch64DAGToDAGISel - AArch64 specific code to select AArch64 machine
42 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
60 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
66 template <signed Low, signed High, signed Scale>
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/freebsd/contrib/elftoolchain/libdwarf/
H A Ddwarf.324 .\" $Id: dwarf.3 3644 2018-10-15 19:55:01Z jkoshy $
48 .Bl -bullet
69 .Bl -tag -width ".Li Dwarf_*" -compact
82 .Bl -tag -width ".Vt Dwarf_Unsigned" -compact
83 .It Vt Dwarf_Abbrev
85 .It Vt Dwarf_Addr
87 .It Vt Dwarf_Arange
89 .It Vt Dwarf_Attribute , Vt Dwarf_P_Attribute
91 .It Vt Dwarf_Bool
93 .It Vt Dwarf_Cie , Vt Dwarf_P_Cie
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H A Ddwarf_object_init.325 .\" $Id: dwarf_object_init.3 3644 2018-10-15 19:55:01Z jkoshy $
32 .Nd allocate a DWARF debug descriptor with application-specific file \
51 instance that uses application-supplied access methods to read file
96 .Bl -tag -width indent
97 .It Vt "Dwarf_Obj_Access_Interface"
99 with a pointer to application-private state.
100 .Bd -literal -offset indent
107 .Bl -tag -width ".Ar methods" -compact
109 This field points to application-specific state that will be passed as
115 .It Vt Dwarf_Obj_Access_Methods
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/freebsd/sbin/conscontrol/
H A Dconscontrol.81 .\"-
2 .\" SPDX-License-Identifer: BSD-2-Clause
59 and a low level console.
60 The low level console is used for kernel
67 Multiple device support is implemented only for the low level console;
77 .Bl -tag -widt
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/freebsd/sys/contrib/device-tree/Bindings/hwmon/
H A Dbaikal,bt1-pvt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/hwmon/baikal,bt1-pvt.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 PVT Sensor
11 - Serge Semin <fancer.lancer@gmail.com>
14 Baikal-T1 SoC provides an embedded process, voltage and temperature
17 which may cause the system instability and even damages. The IP-block
19 control wrapper, which provides a MMIO registers-based access to the
20 sensor core functionality (APB3-bus based) and exposes an additional
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h1 //===-- RISCVISelLowering.h - RISC-V DAG Lowering Interface -----*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that RISC-V uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
30 // clang-format off
37 /// Select with condition operator - This selects between a true value and
57 // Selected as PseudoAddTPRel. Used to emit a TP-relative relocation.
68 // RV64I shifts, directly matching the semantics of the named RISC-V
73 // 32-bit operations from RV64M that can't be simply matched with a pattern
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.td1 //===-- M68kInstrInfo.td - Main M68k Instruction Definition -*- tablegen -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
20 //===----------------------------------------------------------------------===//
25 def MxSDT_Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
27 def MxSDT_Ret : SDTypeProfile<0, -1, [
41 // RES, CCR <- op LHS, RHS
49 // RES, CCR <- op LHS, RHS, CCR
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