Lines Matching +full:low +full:- +full:vt

35 .Bd -ragged -offset indent
40 .Pq SR-IOV :
41 .Bd -ragged -offset indent
45 To compile in support for native PCI-express HotPlug:
46 .Bd -ragged -offset indent
91 or a BAR read access could have function-specific side-effects.
113 driver also includes support for PCI-PCI bridges,
114 various platform-specific Host-PCI bridges,
126 .Bl -tag -width 012345678901234
147 .Bl -tag -width match_buf_len
149 The length, in bytes, of the buffer filled with user-supplied patterns.
151 The number of user-supplied patterns.
153 Pointer to a buffer filled with user-supplied patterns.
162 .Bl -tag -width pd_vendor
203 .Bl -tag -width pc_subvendor
264 .Bl -ohang
302 configuration registers specified by the passed-in
308 .Bl -tag -width pi_width
314 If the specific bus is not found, errno will be set to ENODEV and -1 returned
324 3-byte reads and reads larger than 4 bytes are
335 configuration registers specified in the passed-in
350 device specified in the passed-in
370 the memory-mapped PCI BAR into its address space.
374 .Bl -tag -width Vt struct pcise pbm_sel
375 .It Vt uint64_t	pbm_map_base
381 .It Vt uint64_t pbm_map_length
383 Its .Vt uint64_t value is always multiple of machine pages.
384 .It Vt int64_t pbm_bar_length
386 .It Vt int pbm_bar_off
389 .It Vt struct pcisel pbm_sel
392 .It Vt int pbm_reg
394 .It Vt int pbm_flags
397 .It Vt int pbm_memattr
404 Regular memory-like BAR should be mapped with
410 .Bl -tag -width PCIIO_BAR_MMAP_ACTIVATE
423 Without the flag, read-only mapping is established.
424 Note that it is common for the device registers to have side-effects
438 .Bl -tag
439 .It Vt struct pcisel pbi_sel
441 .It Vt int pbi_op
447 .It Vt uint32_t pbi_bar
449 .It Vt uint32_t pbi_offset
451 .It Vt uint32_t pbi_width
453 1-byte, 2-byte, 4-byte and 8-byte perations are supported.
454 .It Vt uint32_t pbi_value
476 tunable to a non-zero value.
477 .Bl -tag -width indent
479 Ignore any firmware-assigned memory and I/O port resources.
485 Ignore any firmware-assigned bus number registers in PCI-PCI bridges.
488 bus driver and PCI-PCI bridge driver to allocate bus numbers for secondary
489 buses behind PCI-PCI bridges.
491 Ignore any firmware-assigned memory and I/O port resource windows in PCI-PCI
493 This forces the PCI-PCI bridge driver to allocate memory and I/O port resources
496 By default the PCI-PCI bridge driver will allocate windows that
497 contain the firmware-assigned resources devices behind the bridge.
498 In addition, the PCI-PCI bridge driver will suballocate from existing window
505 must be enabled to fully ignore firmware-supplied resource assignments.
506 .It Va hw.pci.default_vgapci_unit Pq Defaults to -1
516 Place devices into a low power state
520 .Bl -tag -width indent
539 Placing a device into a low power state may not reduce power consumption.
546 up non-powered PCI devices after a suspend.
550 devices into a low power state when suspending either the system or individual
552 Normally the D3 state is used as the low power state,
555 Enable support for PCI-express Alternative RID Interpretation.
556 This is often used in conjunction with SR-IOV.
559 firmware-assigned memory or I/O port resources.
571 .Pq MSI-X .
572 MSI-X interrupts can be disabled by setting this tunable to 0.
574 Enable support for PCI-express Electromechanical Interlock.
576 Enable support for native PCI-express HotPlug.
578 MSI and MSI-X interrupts are disabled for certain chipsets known to have
579 broken MSI and MSI-X implementations when this tunable is set.
580 It can be set to zero to permit use of MSI and MSI-X interrupts if the
584 used when creating Virtual Functions via SR-IOV.
589 for any memory or I/O port resources with firmware-assigned ranges that
603 .Bl -tag -width indent
637 .Bl -tag -width -indent
680 .Bl -tag -width /dev/pci -compact
696 Support for device listing and matching was re-implemented by