Lines Matching +full:low +full:- +full:vt
1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
62 /// #0 - The incoming token chain
63 /// #1 - The callee
64 /// #2 - The number of arg bytes the caller pushes on the stack.
65 /// #3 - The number of arg bytes the callee pops off the stack.
66 /// #4 - The value to pass in AL/AX/EAX (optional)
67 /// #5 - The value to pass in DL/DX/EDX (optional)
71 /// #0 - The outgoing token chain
72 /// #1 - The first register result value (optional)
73 /// #2 - The second register result value (optional)
90 /// X86 bit-test instructions.
151 /// Special wrapper used under X86-64 PIC mode for RIP
155 /// Copies a 64-bit value from an MMX vector to the low word
159 /// Copies a 64-bit value from the low word of an XMM vector
163 /// Copies a 32-bit value from the low word of a MMX
167 /// Copies a GPR into the low 32-bit word of a MMX vector
171 /// Extract an 8-bit value from a vector and zero extend it to
175 /// Extract a 16-bit value from a vector and zero extend it to
183 /// Insert the lower 8-bits of a 32-bit value to a vector,
187 /// Insert the lower 16-bits of a 32-bit value to a vector,
191 /// Shuffle 16 8-bit values within a vector.
196 /// Compute Double Block Packed Sum-Absolute-Differences
205 /// Dynamic (non-constant condition) vector blend where only the sign bits
275 /// Floating point reciprocal-sqrt and reciprocal approximation.
281 // AVX-512 reciprocal approximations with a little more precision.
318 // Vector move to low scalar and zero higher vector elements.
327 // Masked version of the above. Used when less than a 128-bit result is
347 // Masked version of above. Used for v2f64->v4f32.
351 // 128-bit vector logical left / right shift
420 // X86-specific multiply by immediate.
443 // Intra-lane alignr.
445 // AVX512 inter-lane alignr.
456 // Shuffle Packed Values at 128-bit granularity.
477 // 3-op Variable Permute (VPERMT2).
493 // Reduce - Perform Reduction Transformation on scalar\packed FP.
498 // RndScale - Round FP Values To Include A Given Number Of Fraction Bits.
555 // We use the target independent ISD::FMA for the non-inverted case.
570 // AVX512-FP16 complex addition and multiplication.
605 // Convert Unsigned/Integer to Floating-Point Value with rounding mode.
639 // Masked versions of above. Used for v2f64->v4f32.
679 // Get a NIST SP800-90B & C compliant random integer and
684 // RDPKRU - Operand 0 is chain. Operand 1 is value for ECX.
685 // WRPKRU - Operand 0 is chain. Operand 1 is value for EDX. Operand 2 is
702 // Conversions between float and half-float.
729 // For avx512-vp2intersect
732 // User level interrupts - testui
763 // RndScale - Round FP Values To Include A Given Number Of Fraction Bits.
777 // Conversions between float and half-float.
784 // WARNING: Only add nodes here if they are strict FP nodes. Non-memory and
785 // non-strict FP nodes should be above FIRST_TARGET_STRICTFP_OPCODE.
793 /// LOCK-prefixed arithmetic read-modify-write instructions.
842 /// and token chain). Memory VT specifies the type to store to.
849 /// specified by the memory VT.
852 /// This instruction implements a fp->int store from FP stack
854 /// chain operand, value to store, address, and glue. The memory VT
860 /// operand, and ptr to load from. The memory VT specifies the type to
866 /// chain operand, value to store, address, and glue. The memory VT
976 //===--------------------------------------------------------------------===//
989 MVT getScalarShiftAmountTy(const DataLayout &, EVT VT) const override { in getScalarShiftAmountTy() argument
1007 /// that contains are placed at 16-byte boundaries while the rest are at
1008 /// 4-byte boundaries.
1021 bool isSafeMemOpType(MVT VT) const override;
1023 bool isMemoryAccessFast(EVT VT, Align Alignment) const;
1027 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment,
1036 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1041 bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, in allowsMemoryAccess() argument
1044 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), in allowsMemoryAccess()
1060 bool preferABDSToABSWithNSW(EVT VT) const override;
1062 bool preferSextInRegOfTruncate(EVT TruncVT, EVT VT,
1066 EVT VT) const override;
1072 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
1103 /// with x86-specific store splitting optimizations.
1119 // save two bitwise instructions and one float-to-int instruction and in isMultiStoresCheaperThanBitsMerge()
1121 // significant benefit because it avoids the float->int domain switch in isMultiStoresCheaperThanBitsMerge()
1147 EVT VT, unsigned ShiftOpc, bool MayTransformRotate,
1169 auto VTIsOk = [](EVT VT) -> bool { in shouldTransformSignedTruncationCheck()
1170 return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 || in shouldTransformSignedTruncationCheck()
1171 VT == MVT::i64; in shouldTransformSignedTruncationCheck()
1184 bool shouldSplatInsEltVarIndex(EVT VT) const override;
1186 bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override { in shouldConvertFpToSat() argument
1189 return Op != ISD::FP_TO_UINT_SAT && isOperationLegalOrCustom(Op, VT); in shouldConvertFpToSat()
1192 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { in convertSetCCLogicToBitwiseLogic() argument
1193 return VT.isScalarInteger(); in convertSetCCLogicToBitwiseLogic()
1196 /// Vector-sized comparisons are fast using PCMPEQ + PMOVMSK or PTEST.
1201 EVT VT) const override;
1314 StringRef Constraint, MVT VT) const override;
1342 /// Add x86-specific opcodes to the default list.
1350 /// register EAX to i16 by referencing its sub-register AX.
1357 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
1361 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1362 /// all instructions that define 32-bit values implicit zero-extend the
1380 EVT VT) const override;
1388 EVT VT) const override;
1401 bool isFPImmLegal(const APFloat &Imm, EVT VT,
1408 bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
1413 bool isVectorClearMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
1424 bool ShouldShrinkFPConstant(EVT VT) const override;
1433 bool isScalarFPTypeInSSEReg(EVT VT) const;
1442 bool convertSelectOfConstantsToMath(EVT VT) const override;
1444 bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
1458 bool isExtractVecEltCheap(EVT VT, unsigned Index) const override {
1459 EVT EltVT = VT.getScalarType();
1466 bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
1480 Register getRegisterByName(const char* RegName, LLT VT,
1514 /// some non-standard address space, and populates the address space and
1525 LegalizeTypeAction getPreferredVectorAction(MVT VT) const override;
1530 EVT VT) const override;
1534 EVT VT) const override;
1537 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
1540 bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
1588 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const override { in getTypeToTransformTo() argument
1589 if (VT == MVT::f80) in getTypeToTransformTo()
1591 return TargetLoweringBase::getTypeToTransformTo(Context, VT); in getTypeToTransformTo()
1597 MVT VT) const override;
1721 return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && in supportSplitCSR()
1722 MF->getFunction().hasFnAttribute(Attribute::NoUnwind); in supportSplitCSR()
1733 EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
1763 // Utility function to emit the low-level va_arg code for X86-64.
1838 SDValue getMOVL(SelectionDAG &DAG, const SDLoc &dl, MVT VT, SDValue V1,
1862 return N->getOpcode() == X86ISD::MGATHER || in classof()
1863 N->getOpcode() == X86ISD::MSCATTER; in classof()
1872 return N->getOpcode() == X86ISD::MGATHER; in classof()
1881 return N->getOpcode() == X86ISD::MSCATTER; in classof()
1886 void createUnpackShuffleMask(EVT VT, SmallVectorImpl<int> &Mask, bool Lo,
1889 /// Similar to unpacklo/unpackhi, but without the 128-bit lane limitation
1891 /// v8iX Lo --> <0, 0, 1, 1, 2, 2, 3, 3>
1892 /// v8iX Hi --> <4, 4, 5, 5, 6, 6, 7, 7>
1893 void createSplat2ShuffleMask(MVT VT, SmallVectorImpl<int> &Mask, bool Lo);