Lines Matching +full:low +full:- +full:vt
1 // WebAssemblyInstrSIMD.td - WebAssembly SIMD codegen support -*- tablegen -*-//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// WebAssembly SIMD operand code-gen constructs.
12 //===----------------------------------------------------------------------===//
29 string asmstr_s = "", bits<32> simdop = -1,
37 string asmstr_s = "", bits<32> simdop = -1> {
44 string asmstr_s = "", bits<32> simdop = -1> {
62 // -2^(n-1) <= Imm < 2^n
63 "return -(1 << ("#SIZE#" - 1)) <= Imm && Imm < (1 << "#SIZE#");"
69 ValueType vt;
82 let vt = v16i8;
83 let int_vt = vt;
94 let vt = v8i16;
95 let int_vt = vt;
107 let vt = v4i32;
108 let int_vt = vt;
120 let vt = v2i64;
121 let int_vt = vt;
133 let vt = v4f32;
145 let vt = v2f64;
157 let vt = v8f16;
172 //===----------------------------------------------------------------------===//
174 //===----------------------------------------------------------------------===//
192 defm : LoadPat<vec.vt, load, "LOAD_V128">;
222 defm : LoadPat<vec.vt,
269 defm : LoadPat<vec.vt, loadpat, inst>;
299 defm : LoadPat<vec.vt, pat, inst>;
307 defm : LoadPat<vec.vt, pat, inst>;
340 def : Pat<(vec.vt (kind (i32 I32:$addr),
341 (vec.vt V128:$vec), (i32 vec.lane_idx:$idx))),
344 def : Pat<(vec.vt (kind (i64 I64:$addr),
345 (vec.vt V128:$vec), (i32 vec.lane_idx:$idx))),
388 defm : StorePat<vec.vt, store, "STORE_V128">;
419 (vec.vt V128:$vec),
424 (vec.vt V128:$vec),
451 //===----------------------------------------------------------------------===//
453 //===----------------------------------------------------------------------===//
459 [(set V128:$dst, (vec.vt pat))],
510 // Match splat(x) -> const.v128(x, ..., x)
512 defvar numEls = !div(vec.vt.Size, vec.lane_bits);
557 def : Pat<(vec.vt (wasm_shuffle (vec.vt V128:$x), (vec.vt V128:$y),
572 def : Pat<(vec.vt (wasm_shuffle (vec.vt V128:$x), (vec.vt V128:$y),
603 [(set (vec.vt V128:$dst),
626 def : Pat<(vec.vt (scalar_to_vector (vec.lane_vt vec.lane_rc:$x))),
629 //===----------------------------------------------------------------------===//
631 //===----------------------------------------------------------------------===//
691 (vec.vt V128:$vec),
719 //===----------------------------------------------------------------------===//
721 //===----------------------------------------------------------------------===//
728 (setcc (vec.vt V128:$lhs), (vec.vt V128:$rhs), cond))],
757 // Non-equality: ne
790 // target-independent expansion of unordered comparisons and ordered ne.
801 //===----------------------------------------------------------------------===//
803 //===----------------------------------------------------------------------===//
809 [(set (vec.vt V128:$dst),
810 (node (vec.vt V128:$lhs), (vec.vt V128:$rhs)))],
827 def : Pat<(node (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
834 [(set (vec.vt V128:$dst),
835 (vec.vt (node (vec.vt V128:$v))))],
849 def : Pat<(vnot (vec.vt V128:$v)), (NOT $v)>;
866 def : Pat<(vec.vt (int_wasm_bitselect
867 (vec.vt V128:$v1), (vec.vt V128:$v2), (vec.vt V128:$c))),
872 def : Pat<(vec.vt (or (and (vec.vt V128:$c), (vec.vt V128:$v1)),
873 (and (vnot V128:$c), (vec.vt V128:$v2)))),
878 def : Pat<(vec.vt (xor (and (xor (vec.vt V128:$v1), (vec.vt V128:$v2)),
879 (vec.vt V128:$c)),
880 (vec.vt V128:$v2))),
885 def : Pat<(vec.vt (xor (and (xor (vec.vt V128:$v1), (vec.vt V128:$v2)),
886 (vnot (vec.vt V128:$c))),
887 (vec.vt V128:$v2))),
892 def : Pat<(vec.vt (vselect
893 (vec.int_vt V128:$c), (vec.vt V128:$v1), (vec.vt V128:$v2))),
902 def : Pat<(select I32:$cond, (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
906 // WebAssembly's select interprets any non-zero value as true, so we can fold
909 (i32 (setne I32:$cond, 0)), (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
914 (i32 (seteq I32:$cond, 0)), (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
918 //===----------------------------------------------------------------------===//
920 //===----------------------------------------------------------------------===//
946 def : Pat<(int_wasm_anytrue (vec.vt V128:$vec)), (ANYTRUE V128:$vec)>;
952 (i32 (int_wasm_alltrue (vec.vt V128:$vec))))],
976 def : Pat<(i32 (and (i32 (intrinsic (vec.vt V128:$x))), (i32 1))), (inst $x)>;
977 def : Pat<(i32 (setne (i32 (intrinsic (vec.vt V128:$x))), (i32 0))), (inst $x)>;
978 def : Pat<(i32 (seteq (i32 (intrinsic (vec.vt V128:$x))), (i32 1))), (inst $x)>;
984 (i32 (int_wasm_bitmask (vec.vt V128:$vec))))],
994 //===----------------------------------------------------------------------===//
996 //===----------------------------------------------------------------------===//
1000 [(set (vec.vt V128:$dst), (node V128:$vec, I32:$x))],
1062 //===----------------------------------------------------------------------===//
1064 //===----------------------------------------------------------------------===//
1120 "return N->getFlags().hasNoUnsignedWrap();">;
1126 (add_nuw (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
1139 // Extending multiplication: extmul_{low,high}_P, extmul_high
1150 [(set (vec.vt V128:$dst), (node
1151 (vec.split.vt V128:$lhs),(vec.split.vt V128:$rhs)))],
1192 //===----------------------------------------------------------------------===//
1193 // Floating-point unary arithmetic
1194 //===----------------------------------------------------------------------===//
1233 // WebAssembly always rounds ties-to-even, so map froundeven to fnearbyint.
1238 //===----------------------------------------------------------------------===//
1239 // Floating-point binary arithmetic
1240 //===----------------------------------------------------------------------===//
1262 // NaN-propagating minimum: min
1265 // NaN-propagating maximum: max
1268 // Pseudo-minimum: pmin
1277 // Pseudo-maximum: pmax
1293 (setolt (vec.vt (bitconvert V128:$rhs)),
1294 (vec.vt (bitconvert V128:$lhs))),
1298 (setolt (vec.vt (bitconvert V128:$lhs)),
1299 (vec.vt (bitconvert V128:$rhs))),
1318 //===----------------------------------------------------------------------===//
1320 //===----------------------------------------------------------------------===//
1326 [(set (vec.vt V128:$dst), (vec.vt (op (arg.vt V128:$vec))))],
1389 SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins),
1390 [(set (vec.split.vt V128:$dst), (vec.split.vt (int_wasm_narrow_signed
1391 (vec.vt V128:$low), (vec.vt V128:$high))))],
1392 name#"_s\t$dst, $low, $high", name#"_s", baseInst>;
1394 SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins),
1395 [(set (vec.split.vt V128:$dst), (vec.split.vt (int_wasm_narrow_unsigned
1396 (vec.vt V128:$low), (vec.vt V128:$high))))],
1397 name#"_u\t$dst, $low, $high", name#"_u", !add(baseInst, 1)>;
1416 def : Pat<(t1.vt (bitconvert (t2.vt V128:$v))), (t1.vt V128:$v)>;
1428 // f64x2 <-> f32x4 conversions
1451 //===----------------------------------------------------------------------===//
1452 // Saturating Rounding Q-Format Multiplication
1453 //===----------------------------------------------------------------------===//
1458 //===----------------------------------------------------------------------===//
1460 //===----------------------------------------------------------------------===//
1468 //===----------------------------------------------------------------------===//
1469 // Relaxed floating-point to int conversions
1470 //===----------------------------------------------------------------------===//
1475 [(set (vec.vt V128:$dst), (vec.vt (op (arg.vt V128:$vec))))],
1488 //===----------------------------------------------------------------------===//
1489 // Relaxed (Negative) Multiply-Add (madd/nmadd)
1490 //===----------------------------------------------------------------------===//
1495 [(set (vec.vt V128:$dst), (int_wasm_relaxed_madd
1496 (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
1501 [(set (vec.vt V128:$dst), (int_wasm_relaxed_nmadd
1502 (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
1511 //===----------------------------------------------------------------------===//
1513 //===----------------------------------------------------------------------===//
1518 [(set (vec.vt V128:$dst), (int_wasm_relaxed_laneselect
1519 (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
1529 //===----------------------------------------------------------------------===//
1530 // Relaxed floating-point min and max.
1531 //===----------------------------------------------------------------------===//
1537 [(set (vec.vt V128:$dst),
1538 (node (vec.vt V128:$lhs), (vec.vt V128:$rhs)))],
1552 //===----------------------------------------------------------------------===//
1554 //===----------------------------------------------------------------------===//
1560 //===----------------------------------------------------------------------===//
1562 //===----------------------------------------------------------------------===//
1579 //===----------------------------------------------------------------------===//
1581 //===----------------------------------------------------------------------===//