| /freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
4 The cache bindings explained below are Devicetree Specification compliant
8 - compatible : Should include one of the following:
9 "fsl,b4420-l2-cache-controller"
10 "fsl,b4860-l2-cache-controller"
11 "fsl,bsc9131-l2-cache-controller"
12 "fsl,bsc9132-l2-cache-controller"
13 "fsl,c293-l2-cache-controller"
14 "fsl,mpc8536-l2-cache-controller"
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/cache/ |
| H A D | freescale-l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
4 The cache bindings explained below are Devicetree Specification compliant
8 - compatible : Should include one of the following:
9 "fsl,b4420-l2-cache-controller"
10 "fsl,b4860-l2-cache-controller"
11 "fsl,bsc9131-l2-cache-controller"
12 "fsl,bsc9132-l2-cache-controller"
13 "fsl,c293-l2-cache-controller"
14 "fsl,mpc8536-l2-cache-controller"
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/x86/amdzen3/ |
| H A D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
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| H A D | recommended.json | 4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
12 "BriefDescription": "All L1 Data Cache Accesses",
17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 Cache HWPF",
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/x86/amdzen1/ |
| H A D | cache.json | 5 …tch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheab…
15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
20 …escription": "The number of 64 byte instruction cache line fulfilled from system memory or another…
25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
35 … instruction stream was being modified by another processor in an MP system - typically a highly u…
52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
58 …"IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cach…
64 … due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC ev…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
[all …]
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| H A D | recommended.json | 4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
12 "BriefDescription": "All L1 Data Cache Accesses",
17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 HWPF",
[all …]
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| /freebsd/sys/powerpc/mpc85xx/ |
| H A D | mpc85xx_cache.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
41 * - mbar
42 * - isync
43 * - write
44 * - read
45 * - mbar
55 {"fsl,8540-l2-cache-controller", 1},
56 {"fsl,8541-l2-cache-controller", 1},
57 {"fsl,8544-l2-cache-controller", 1},
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/x86/amdzen2/ |
| H A D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
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| H A D | recommended.json | 4 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
12 "BriefDescription": "All L1 Data Cache Accesses",
17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
41 "BriefDescription": "All L2 Cache Misses",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59 "BriefDescription": "L2 Cache Misses from L2 HWPF",
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/x86/goldmont/ |
| H A D | cache.json | 12 "BriefDescription": "L1 Cache evictions for dirty data",
17 …"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache …
22 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
27 …s not the same as the total number of cycles spent retrieving instruction cache lines from the mem…
37 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
41 "BriefDescription": "L2 cache request misses",
46 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
51 "BriefDescription": "L2 cache requests",
56 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
68 … loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit…
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/x86/goldmontplus/ |
| H A D | cache.json | 14 "BriefDescription": "L1 Cache evictions for dirty data",
21 …"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache …
26 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
33 …s not the same as the total number of cycles spent retrieving instruction cache lines from the mem…
45 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
49 "BriefDescription": "L2 cache request misses",
56 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
61 "BriefDescription": "L2 cache requests",
68 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
81 … loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit…
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a510/ |
| H A D | cache.json | 102 …L2 cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this ev…
105 …L2 cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this ev…
108 …": "L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher that…
111 …": "L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher that…
114 …L2 cache write streaming mode. This event counts for each cycle where the core is in write streami…
117 …L2 cache write streaming mode. This event counts for each cycle where the core is in write streami…
120 …"PublicDescription": "L1 data cache entering write streaming mode. This event counts for each entr…
123 …"BriefDescription": "L1 data cache entering write streaming mode. This event counts for each entry…
126 …cache write streaming mode. This event counts for each cycle where the core is in write streaming …
129 …cache write streaming mode. This event counts for each cycle where the core is in write streaming …
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/powerpc/power8/ |
| H A D | cache.json | 5 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
6 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …
11 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…
12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch…
17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…
23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand …
24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…
29 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)",
35 …"BriefDescription": "The processor's data cache was reloaded from a localtion other than the local…
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/x86/broadwellde/ |
| H A D | cache.json | 8 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
28 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
55 "BriefDescription": "Not rejected writebacks that hit L2 cache",
60 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
65 "BriefDescription": "L2 cache lines filling L2",
70 …"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does…
75 "BriefDescription": "L2 cache lines in E state filling L2",
80 …licDescription": "This event counts the number of L2 cache lines in the Exclusive state filling th…
85 "BriefDescription": "L2 cache lines in I state filling L2",
90 …licDescription": "This event counts the number of L2 cache lines in the Invalidate state filling t…
[all …]
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| /freebsd/lib/libpmc/ |
| H A D | pmc.corei7.3 | 44 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
60 .%N "Order Number: 253669-033US"
67 Not all CPUs in this family implement fixed-function counters.
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
89 Configure the Off-core Response bits.
90 .Bl -tag -width indent
95 Does not count L2 data read prefetches or instruction fetches.
[all …]
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| H A D | pmc.westmere.3 | 44 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
60 .%N "Order Number: 253669-033US"
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
86 .Bl -tag -width indent
88 Configure the Off-core Response bits.
89 .Bl -tag -width indent
94 Does not count L2 data read prefetches or
99 Does not count L2 RFO.
[all …]
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| H A D | pmc.sandybridgexeon.3 | 45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
61 .%N "Order Number: 253669-043US"
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
89 Configure the Off-core Response bits.
90 .Bl -tag -width indent
94 Does not count L2 data read prefetches or instruction fetches.
98 Does not count L2 RFO prefetches.
[all …]
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| H A D | pmc.ivybridgexeon.3 | 45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
60 .%N "Order Number: 325462-045US"
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
86 .Bl -tag -width indent
88 Configure the Off-core Response bits.
89 .Bl -tag -width indent
93 Does not count L2 data read prefetches or instruction fetches.
97 Does not count L2 RFO prefetches.
[all …]
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| H A D | pmc.haswell.3 | 45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
61 .%N "Order Number: 325462-045US"
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
89 Configure the Off-core Response bits.
90 .Bl -tag -width indent
95 Does not count L2 data read prefetches or instruction fetches.
99 Does not count L2 RFO prefetches.
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/ |
| H A D | cache.json | 3 …ts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a…
10 …L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L…
33 …The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 …
37 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
44 … "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door request…
48 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe…
55 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front d…
60 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a p…
67 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a miss from a front …
72 …"BriefDescription": "Counts the number of L2 Cache accesses that miss the L2 and get rejected. Cou…
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a65/ |
| H A D | cache.json | 111 …"Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which…
114 …"Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which…
117 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event …
120 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event …
123 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c…
126 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c…
141 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
144 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
147 … 3 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
150 … 3 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a76-n1/ |
| H A D | cache.json | 3 "PublicDescription": "This event counts any instruction fetch which misses in the cache.",
7 …"PublicDescription": "This event counts any refill of the instruction L1 TLB from the L2 TLB. This…
15 …r store operation or page table walk access which looks up in the L1 data cache. In particular, an…
19 …"PublicDescription": "This event counts any refill of the data L1 TLB from the L2 TLB. This includ…
23 …on cache access or Level 0 Macro-op cache access. This event counts any instruction fetch which ac…
27 …t counts any write-back of data from the L1 data cache to L2 or L3. This counts both victim line e…
31 … from L1 which looks up in the L2 cache, and any write-back from the L1 to the L2. Snoops from out…
35 …L2 data cache refill. This event counts any cacheable transaction from L1 which causes data to be …
39 …-back of data from the L2 cache to outside the core. This includes snoops to the L2 which return d…
43 …ent counts any full cache line write into the L2 cache which does not cause a linefill, including …
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/x86/ivybridge/ |
| H A D | cache.json | 8 "PublicDescription": "Counts the number of lines brought into the L1 data cache.",
56 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
65 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
70 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
75 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
80 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
85 …iption": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from…
95 "BriefDescription": "L2 cache lines filling L2",
100 "PublicDescription": "L2 cache lines filling L2.",
105 "BriefDescription": "L2 cache lines in E state filling L2",
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/x86/tigerlake/ |
| H A D | cache.json | 3 "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
9 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
38 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
44 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re…
55 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
72 "BriefDescription": "L2 cache lines filling L2",
78 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover …
83 …"BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cac…
89 …iption": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fi…
94 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered…
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm64/amd/ |
| H A D | amd-seattle-cpus.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 #address-cells = <0x1>;
6 #size-cells = <0x0>;
8 cpu-map {
45 compatible = "arm,cortex-a57";
47 enable-method = "psci";
49 i-cache-size = <0xC000>;
50 i-cache-line-size = <64>;
51 i-cache-sets = <256>;
52 d-cache-size = <0x8000>;
[all …]
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