Lines Matching +full:l2 +full:- +full:cache

45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
60 .%N "Order Number: 325462-045US"
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
86 .Bl -tag -width indent
88 Configure the Off-core Response bits.
89 .Bl -tag -width indent
93 Does not count L2 data read prefetches or instruction fetches.
97 Does not count L2 RFO prefetches.
100 Does not count L2 code read prefetches.
104 Counts the number of data cacheline reads generated by L2 prefetchers.
106 Counts the number of RFO requests generated by L2 prefetchers.
108 Counts the number of code reads generated by L2 prefetchers.
110 L2 prefetcher to L3 for loads.
112 RFO requests generated by L2 prefetcher
114 L2 prefetcher to L3 for instruction fetches.
126 M-state initial lookup stat in L3.
128 E-state.
130 S-state.
132 F-state.
136 No details on snoop-related information.
145 A snoop was needed and it hits in at least one snooped cache.
146 Hit denotes a cache-line was valid before snoop effect.
157 A snoop was needed and it HitM-ed in local or remote cache.
158 HitM denotes a cache-line was in modified state before effect as a results of snoop.
164 Target was non-DRAM system address.
172 Configure the PMC to count the number of de-asserted to asserted
199 .Bl -tag -width indent
205 Speculative cache-line split load uops dispatched to L1D.
208 Speculative cache-line split Store- address uops dispatched to L1D.
228 Number of flags-merge uops allocated.
243 Demand Data Read requests that hit L2 cache.
246 Counts any demand and L1 HW prefetch data load requests to L2.
249 Counts the number of store RFO requests that hit the L2 cache.
252 Counts the number of store RFO requests that miss the L2 cache.
255 Counts all L2 store RFO requests.
258 Number of instruction fetches that hit the L2 cache.
261 Number of instruction fetches that missed the L2 cache.
264 Counts all L2 code requests.
267 Counts all L2 HW prefetcher requests that hit L2.
270 Counts all L2 HW prefetcher requests that missed L2.
273 Counts all L2 HW prefetcher requests.
276 RFOs that miss cache lines.
279 RFOs that hit cache lines in M state.
282 RFOs that access cache lines in any state.
288 Not rejected writebacks from L1D to L2 cache lines in E state.
291 Not rejected writebacks from L1D to L2 cache lines in M state.
294 Not rejected writebacks from L1D to L2 cache lines in any state.
297 This event counts requests originating from the core that reference a cache
298 line in the last level cache.
301 This event counts each cache miss condition for references to the last level
302 cache.
333 Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.
336 Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.
339 Counts the number of lines brought into the L1 data cache.
383 Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.
438 Number of Instruction Cache, Streaming Buffer and Victim Cache Misses.
451 Number of cache load STLB hits.
515 Count number of non-delivered uops to RAT per thread.
559 Cycles stalled due to re-order buffer full.
562 Cycles with pending L2 miss loads.
574 Cycles with pending L1 cache miss loads.
603 Counts total number of uops to be executed per-thread each cycle.
607 Counts total number of uops to be executed per-core each cycle.
611 Off-core Response Performance Monitoring.
616 Off-core Response Performance Monitoring.
621 DTLB flush attempts of the thread- specific entries.
636 Number of assists associated with 256-bit AVX store operations.
639 Number of transitions from AVX- 256 to legacy SSE when penalty applicable.
642 Number of transitions from SSE to AVX-256 when penalty applicable.
645 Counts the number of micro-ops retired, Use cmask=1 and invert to count
656 Number of self-modifying-code machine clears detected.
740 Count retired load uops that were split across a cache line.
743 Count retired store uops that were split across a cache line.
752 Retired load uops with L1 cache hits as data sources.
756 Retired load uops with L2 cache hits as data sources.
766 to preceding miss to the same cache line with data not ready.
769 Retired load uops which data sources were LLC hit and cross-core snoop
770 missed in on-pkg core cache.
774 Retired load uops which data sources were LLC and cross-core snoop hits in
775 on-pkg core cache.
797 Retired load uops whose data source was forwards from a remote cache.
800 Number of front end re-steers due to BPU misprediction.
803 Demand Data Read requests that access L2 cache.
806 RFO requests that access L2 cache.
809 L2 cache accesses when fetching instructions.
812 Any MLC or LLC HW prefetch accessing L2, including rejects.
815 L1D writebacks that access L2 cache.
818 L2 fill requests that access L2 cache.
821 L2 writebacks that access L2 cache.
824 Transactions accessing L2 pipe.
827 L2 cache lines in I state filling L2.
831 L2 cache lines in S state filling L2.
835 L2 cache lines in E state filling L2.
839 L2 cache lines filling L2.
843 Clean L2 cache lines evicted by demand.
846 Dirty L2 cache lines evicted by demand.
849 Clean L2 cache lines evicted by the MLC prefetcher.
852 Dirty L2 cache lines evicted by the MLC prefetcher.
855 Dirty L2 cache lines filling the L2.
883 .An -nosplit