Lines Matching +full:l2 +full:- +full:cache
8 "PublicDescription": "Counts the number of lines brought into the L1 data cache.",
56 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
65 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
70 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
75 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
80 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
85 …iption": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from…
95 "BriefDescription": "L2 cache lines filling L2",
100 "PublicDescription": "L2 cache lines filling L2.",
105 "BriefDescription": "L2 cache lines in E state filling L2",
110 "PublicDescription": "L2 cache lines in E state filling L2.",
115 "BriefDescription": "L2 cache lines in I state filling L2",
120 "PublicDescription": "L2 cache lines in I state filling L2.",
125 "BriefDescription": "L2 cache lines in S state filling L2",
130 "PublicDescription": "L2 cache lines in S state filling L2.",
135 "BriefDescription": "Clean L2 cache lines evicted by demand",
140 "PublicDescription": "Clean L2 cache lines evicted by demand.",
145 "BriefDescription": "Dirty L2 cache lines evicted by demand",
150 "PublicDescription": "Dirty L2 cache lines evicted by demand.",
155 "BriefDescription": "Dirty L2 cache lines filling the L2",
160 "PublicDescription": "Dirty L2 cache lines filling the L2.",
165 "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch",
170 "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.",
175 "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch",
180 "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.",
185 "BriefDescription": "L2 code requests",
190 "PublicDescription": "Counts all L2 code requests.",
200 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
205 "BriefDescription": "Requests from L2 hardware prefetchers",
210 "PublicDescription": "Counts all L2 HW prefetcher requests.",
215 "BriefDescription": "RFO requests to L2 cache",
220 "PublicDescription": "Counts all L2 store RFO requests.",
225 "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
230 "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
235 "BriefDescription": "L2 cache misses when fetching instructions",
240 "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
245 "BriefDescription": "Demand Data Read requests that hit L2 cache",
250 "PublicDescription": "Demand Data Read requests that hit L2 cache.",
255 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",
260 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
265 "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",
270 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
275 "BriefDescription": "RFO requests that hit L2 cache",
280 "PublicDescription": "RFO requests that hit L2 cache.",
285 "BriefDescription": "RFO requests that miss L2 cache",
290 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
295 "BriefDescription": "RFOs that access cache lines in any state",
300 "PublicDescription": "RFOs that access cache lines in any state.",
305 "BriefDescription": "RFOs that hit cache lines in M state",
310 "PublicDescription": "RFOs that hit cache lines in M state.",
315 "BriefDescription": "RFOs that miss cache lines",
320 "PublicDescription": "RFOs that miss cache lines.",
325 "BriefDescription": "L2 or LLC HW prefetches that access L2 cache",
330 "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.",
335 "BriefDescription": "Transactions accessing L2 pipe",
340 "PublicDescription": "Transactions accessing L2 pipe.",
345 "BriefDescription": "L2 cache accesses when fetching instructions",
350 "PublicDescription": "L2 cache accesses when fetching instructions.",
355 "BriefDescription": "Demand Data Read requests that access L2 cache",
360 "PublicDescription": "Demand Data Read requests that access L2 cache.",
365 "BriefDescription": "L1D writebacks that access L2 cache",
370 "PublicDescription": "L1D writebacks that access L2 cache.",
375 "BriefDescription": "L2 fill requests that access L2 cache",
380 "PublicDescription": "L2 fill requests that access L2 cache.",
385 "BriefDescription": "L2 writebacks that access L2 cache",
390 "PublicDescription": "L2 writebacks that access L2 cache.",
395 "BriefDescription": "RFO requests that access L2 cache",
400 "PublicDescription": "RFO requests that access L2 cache.",
415 "BriefDescription": "Core-originated cacheable demand requests missed LLC",
420 …"PublicDescription": "This event counts each cache miss condition for references to the last level…
425 "BriefDescription": "Core-originated cacheable demand requests that refer to LLC",
430 …nt counts requests originating from the core that reference a cache line in the last level cache.",
435 …": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.",
455 …tired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.",
480 …"PublicDescription": "Retired load uops whose data source was local memory (cross-socket snoop not…
485 …ces were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not…
495 "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
505 "BriefDescription": "Retired load uops which data sources following L1 data-cache miss.",
515 "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
525 "BriefDescription": "Retired load uops with L2 cache misses as data sources.",
545 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
782 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
842 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
890 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
938 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
998 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
1046 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
1058 …t include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to…
1070 … "Counts requests where the address of an atomic lock instruction spans a cache line boundary or t…
1082 "BriefDescription": "Counts non-temporal stores",