Lines Matching +full:l2 +full:- +full:cache

44 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
60 .%N "Order Number: 253669-033US"
67 Not all CPUs in this family implement fixed-function counters.
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
89 Configure the Off-core Response bits.
90 .Bl -tag -width indent
95 Does not count L2 data read prefetches or instruction fetches.
99 Does not count L2 RFO.
103 Does not count L2 code read prefetches.
106 Counts the number of data cacheline reads generated by L2 prefetchers.
108 Counts the number of RFO requests generated by L2 prefetchers.
110 Counts the number of code reads generated by L2 prefetchers.
113 I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences,
116 L3 Hit: local or remote home requests that hit L3 cache in the uncore
119 L3 Hit: local or remote home requests that hit L3 cache in the uncore
123 L3 Hit: local or remote home requests that hit L3 cache in the uncore
127 L3 Miss: local homed requests that missed the L3 cache and was serviced
131 L3 Miss: remote home requests that missed the L3 cache and were serviced
134 L3 Miss: local home requests that missed the L3 cache and were serviced
137 Non-DRAM requests that were serviced by IOH.
144 Configure the PMC to count the number of de-asserted to asserted
171 .Bl -tag -width indent
177 Counts number of loads delayed with at-Retirement block code.
196 Number of cache load STLB hits
199 Number of DTLB cache load misses where the low part of the linear to
206 Counts the number of instructions with an architecturally-visible store
211 Counts the number of instructions with an architecturally-visible store
252 missed the L1, L2 and L3 caches and HIT in a remote socket's cache.
257 missed the L1, L2 and L3 caches and was remotely homed.
258 This includes both DRAM access and HITM in a remote socket's cache
263 missed the L1, L2 and L3 caches and required a local socket memory
270 missed the L1, L2 and L3 caches and to perform I/O.
328 one-cycle delayed staging latch before it is written into the LB.
368 decode enough instructions per cycle to sustain the 4-wide pipeline.
377 Counts number of loads that hit the L2 cache.
378 L2 loads include both L1D demand misses as well as L1D prefetches.
379 L2 loads can be rejected for various reasons.
383 Counts the number of loads that miss the L2 cache.
384 L2 loads include both L1D demand misses as well as L1D prefetches.
387 Counts all L2 load requests.
388 L2 loads include both L1D demand misses as well as L1D prefetches.
391 Counts the number of store RFO requests that hit the L2 cache.
392 L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.
397 Counts the number of store RFO requests that miss the L2 cache.
398 L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.
401 Counts all L2 store RFO requests.
402 L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.
405 Counts number of instruction fetches that hit the L2 cache.
406 L2 instruction fetches include both L1I demand misses as well as L1I instruction
410 Counts number of instruction fetches that miss the L2 cache.
411 L2 instruction fetches include both L1I demand misses as well as L1I instruction
416 L2 instruction fetches include both L1I demand misses as well as L1I instruction prefetches.
419 Counts L2 prefetch hits for both code and data.
422 Counts L2 prefetch misses for both code and data.
425 Counts all L2 prefetches for both code and data.
428 Counts all L2 misses for both code and data.
431 Counts all L2 requests for both code and data.
434 Counts number of L2 data demand loads where the cache line to be loaded is
435 in the I (invalid) state, i.e. a cache miss.
436 L2 demand loads are both L1D demand misses and L1D prefetches.
439 Counts number of L2 data demand loads where the cache line to be loaded is
441 L2 demand loads are both L1D demand misses and L1D prefetches.
444 Counts number of L2 data demand loads where the cache line to be loaded is
446 L2 demand loads are both L1D demand misses and L1D prefetches.
449 Counts number of L2 data demand loads where the cache line to be loaded is
451 L2 demand loads are both L1D demand misses and L1D prefetches.
454 Counts all L2 data demand requests.
455 L2 demand loads are both L1D demand misses and L1D prefetches.
458 Counts number of L2 prefetch data loads where the cache line to be loaded is
459 in the I (invalid) state, i.e. a cache miss.
462 Counts number of L2 prefetch data loads where the cache line to be loaded is
468 Counts number of L2 prefetch data loads where the cache line to be loaded is
472 Counts number of L2 prefetch data loads where the cache line to be loaded is
476 Counts all L2 prefetch requests.
479 Counts all L2 data requests.
482 Counts number of L2 demand store RFO requests where the cache line to be
483 loaded is in the I (invalid) state, i.e, a cache miss.
488 Counts number of L2 store RFO requests where the cache line to be loaded is
494 Counts number of L2 store RFO requests where the cache line to be loaded is
500 Counts number of L2 store RFO requests where the cache line to be loaded is
506 Counts all L2 store RFO requests.
511 Counts number of L2 demand lock RFO requests where the cache line to be
512 loaded is in the I (invalid) state, i.e. a cache miss.
515 Counts number of L2 lock RFO requests where the cache line to be loaded is
519 Counts number of L2 demand lock RFO requests where the cache line to be
523 Counts number of L2 demand lock RFO requests where the cache line to be
527 Counts number of L2 demand lock RFO requests where the cache line to be
531 Counts all L2 demand lock RFO requests.
534 Counts number of L1 writebacks to the L2 where the cache line to be written
535 is in the I (invalid) state, i.e. a cache miss.
538 Counts number of L1 writebacks to the L2 where the cache line to be written
542 Counts number of L1 writebacks to the L2 where the cache line to be written
546 Counts number of L1 writebacks to the L2 where the cache line to be written
550 Counts all L1 writebacks to the L2.
553 This event counts requests originating from the core that reference a cache
554 line in the last level cache.
555 The event count includes speculative traffic but excludes cache line fills
556 due to a L2 hardware-prefetch.
557 Because cache hierarchy, cache sizes and other implementation-specific
559 see Table A-1
562 This event counts each cache miss condition for references to the last level
563 cache.
564 The event count may include speculative traffic but excludes cache
565 line fills due to L2 hardware-prefetches.
566 Because cache hierarchy, cache sizes and other implementation-specific
568 see Table A-1
574 see Table A-1
578 see Table A-1
581 Counts L1 data cache read requests where the cache line to be loaded is in
582 the I (invalid) state, i.e. the read request missed the cache.
586 Counts L1 data cache read requests where the cache line to be loaded is in
591 Counts L1 data cache read requests where the cache line to be loaded is in
596 Counts L1 data cache read requests where the cache line to be loaded is in
601 Counts L1 data cache read requests.
605 Counts L1 data cache store RFO requests where the cache line to be loaded is
610 Counts L1 data cache store RFO requests where the cache line to be loaded is
615 Counts L1 data cache store RFO requests where cache line to be loaded is in
620 Counts retired load locks that hit in the L1 data cache or hit in an already
623 The initial load will pull the lock into the L1 data cache.
627 Counts L1 data cache retired load locks that hit the target cache line in
632 Counts L1 data cache retired load locks that hit the target cache line in
637 Counts L1 data cache retired load locks that hit the target cache line in
643 cache, including all loads and stores with any memory types.
647 The event does not include non- memory accesses, such as I/O accesses.
672 Counts load operations sent to the L1 data cache while a previous SSE
673 prefetch instruction to the same cache line has started prefetching but has
695 Counts the number of lines brought into the L1 data cache.
699 Counts the number of modified lines brought into the L1 data cache.
703 Counts the number of modified lines evicted from the L1 data cache due to
708 Counts the number of modified lines evicted from the L1 data cache due to
721 Cycle count during which the L1D and L2 are locked.
723 operation that spans two cache lines, or a page walk from an uncacheable
726 L1D and L2 locks have a very high performance penalty and it is highly recommended to
730 Counts the number of cycles that cacheline in the L1 data cache unit is
738 Counts all instruction fetches that hit the L1 instruction cache.
741 Counts all instruction fetches that miss the L1I cache.
742 This includes instruction cache misses, streaming buffer misses, victim cache misses and
752 Cycle counts for which an instruction fetch stalls due to a L1I cache miss,
819 This includes only instructions and not micro-op branches.
843 Counts mispredicted non-indirect near calls executed, (should always be 0).
868 Does not include stalls due to SuperQ (off core) queue full, too many cache
878 operations in the pipe (possibly load and store operations that miss the L2
879 cache, or instructions dependent upon instructions further down the pipeline
888 The stall ends when a store instruction commits its data to the cache or memory.
891 Counts the cycles of stall due to re- order buffer full.
895 floating-point unit (FPU) control word.
907 Counts the number of instructions decoded that are macro-fused but not
913 based on a static scheme and dynamic data provided by the L2 Branch
922 Counts the number of micro-ops delivered by loop stream detector
958 Invert=1 to count P0-4 stalled cycles Use Cmask=1, Edge=1, Invert=1 to count
959 P0-4 stalls.
966 Use Cmask=1 for active cycles; Cmask=0 for weighted cycles; Use CMask=1, Invert=1 to count P0-4 sta…
967 cycles Use Cmask=1, Edge=1, Invert=1 to count P0-4 stalls.
977 Counts number of cycles the SQ is full to handle off-core requests.
980 see Section 30.6.1.3, Off-core Response Performance Monitoring in the
997 see Section 30.6.1.3, Off-core Response Performance Monitoring in the
1002 See Table A-1
1016 sub-operations of complex floating point instructions like transcendental
1020 Counts the number of micro-ops retired, (macro-fused=1, micro- fused=2,
1022 Most instructions are composed of one or two micro-ops.
1031 Counts number of macro-fused uops retired.
1041 Self-modifying code causes a sever penalty in all Intel 64 and IA-32
1043 The modified cache line is written back to the L2 and L3caches.
1046 See Table A-1
1058 See Table A-1
1064 Counts SIMD packed single-precision floating point Uops retired.
1067 Counts SIMD calar single-precision floating point Uops retired.
1070 Counts SIMD packed double- precision floating point Uops retired.
1073 Counts SIMD scalar double-precision floating point Uops retired.
1076 Counts 128-bit SIMD vector integer Uops retired.
1083 Counts number of retired loads that hit the L1 data cache.
1086 Counts number of retired loads that hit the L2 data cache.
1090 cache.
1093 Counts number of retired loads that hit in a sibling core's L2 (on die core).
1098 Counts number of retired loads that miss the L3 cache.
1103 in an allocated line fill buffer and will soon be committed to cache.
1114 Counts the first floating-point instruction following any MMX instruction.
1116 floating-point and MMX technology states.
1119 Counts the first MMX instruction following a floating-point instruction.
1121 floating-point and MMX technology states.
1127 floating-point and MMX technology states.
1165 not allow new micro-ops to enter the out-of-order pipeline.
1167 the same cycle and prevent the stalled micro-ops from entering the pipe.
1168 In such a case, micro-ops retry entering the execution pipe in the next
1169 cycle and the ROB-read port stall is counted again.
1178 read port stalls occurred, which did not allow new micro-ops to enter the
1181 Cycles floating-point unit (FPU) status word stalls occurred.
1190 segment occurs, a stall occurs in the front-end of the pipeline until the
1233 Counts L2 load operations due to HW prefetch or demand loads.
1236 Counts L2 RFO operations due to HW prefetch or demand RFOs.
1239 Counts L2 instruction fetch operations due to HW prefetch or demand ifetch.
1242 Counts L2 prefetch operations.
1245 Counts L1D writeback operations to the L2.
1248 Counts L2 cache line fill operations due to load, RFO, L1D writeback or
1252 Counts L2 writeback operations to the L3.
1255 Counts all L2 cache operations.
1258 Counts the number of cache lines allocated in the L2 cache in the S (shared)
1262 Counts the number of cache lines allocated in the L2 cache in the E
1266 Counts the number of cache lines allocated in the L2 cache.
1269 Counts L2 clean cache lines evicted by a demand request.
1272 Counts L2 dirty (modified) cache lines evicted by a demand request.
1275 Counts L2 clean cache line evicted by a prefetch request.
1278 Counts L2 modified cache line evicted by a prefetch request.
1281 Counts all L2 cache lines evicted for any reason.
1284 Counts the number of SQ lock splits across a cache line.
1292 micro-code assist intervention.
1300 Counts number of floating point micro-code assist when the output value
1304 Counts number of floating point micro-code assist when the input value (one
1331 .Bl -tag -width indent
1389 Counts number of L2 store RFO requests where the cache line to be loaded is
1398 Counts micro-ops decoded by decoder 0.
1401 Counts L1 data cache store RFO requests where the cache line to be loaded is
1407 Counts L1 data cache store RFO requests.
1411 Number of DTLB cache misses where the low part of the linear to physical
1422 Counts number of SSE NTA prefetch/weakly-ordered instructions which missed
1423 the L1 data cache.
1433 The Extended Page Directory cache is used by Virtual Machine operating
1444 Does not include L2 prefetch requests.
1449 Does not include L2 prefetch requests.
1454 Does not include L2 prefetch requests.
1459 Include L2 prefetch requests.
1463 Instruction Fetche unit victim cache full.
1466 L1 Instruction cache evictions.
1493 Does not count L2 prefetch requests.
1497 Does not count L2 prefetch requests.
1501 Does not count L2 prefetch requests.
1505 Includes L2 prefetch requests.
1509 Includes L2 prefetch requests.
1533 Counts number of TPR writes one or two micro-ops.
1537 Counts the number of macro-fusion assists
1538 Counts SIMD packed single- precision floating point Uops retired.
1544 Count L2 HW prefetcher detector hits
1547 Count L2 HW prefetcher allocations
1550 Count L2 HW data prefetcher triggered
1553 Count L2 HW code prefetcher triggered
1556 Count L2 HW DCA prefetcher triggered
1559 Count L2 HW prefetcher kick started
1562 Counts the number of L2 secondary misses that hit the Super Queue.
1565 Counts the number of L2 secondary misses during the Super Queue filling L2.
1571 Counts the number of SQ L2 fills dropped due to L2 busy.