xref: /freebsd/lib/libpmc/pmu-events/arch/powerpc/power8/cache.json (revision 3a3deb00a5e449c9478156b162dfa10ec82a2a3f)
1959826caSMatt Macy[
2*3a3deb00SEd Maste  {
3959826caSMatt Macy    "EventCode": "0x4c048",
4959826caSMatt Macy    "EventName": "PM_DATA_FROM_DL2L3_MOD",
5959826caSMatt Macy    "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
6959826caSMatt Macy    "PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
7959826caSMatt Macy  },
8*3a3deb00SEd Maste  {
9959826caSMatt Macy    "EventCode": "0x3c048",
10959826caSMatt Macy    "EventName": "PM_DATA_FROM_DL2L3_SHR",
11959826caSMatt Macy    "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
12959826caSMatt Macy    "PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
13959826caSMatt Macy  },
14*3a3deb00SEd Maste  {
15959826caSMatt Macy    "EventCode": "0x3c04c",
16959826caSMatt Macy    "EventName": "PM_DATA_FROM_DL4",
17959826caSMatt Macy    "BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load",
18959826caSMatt Macy    "PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
19959826caSMatt Macy  },
20*3a3deb00SEd Maste  {
21959826caSMatt Macy    "EventCode": "0x1c042",
22959826caSMatt Macy    "EventName": "PM_DATA_FROM_L2",
23959826caSMatt Macy    "BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand load",
24959826caSMatt Macy    "PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
25959826caSMatt Macy  },
26*3a3deb00SEd Maste  {
27959826caSMatt Macy    "EventCode": "0x200fe",
28959826caSMatt Macy    "EventName": "PM_DATA_FROM_L2MISS",
29959826caSMatt Macy    "BriefDescription": "Demand LD - L2 Miss (not L2 hit)",
30959826caSMatt Macy    "PublicDescription": ""
31959826caSMatt Macy  },
32*3a3deb00SEd Maste  {
33959826caSMatt Macy    "EventCode": "0x1c04e",
34959826caSMatt Macy    "EventName": "PM_DATA_FROM_L2MISS_MOD",
35959826caSMatt Macy    "BriefDescription": "The processor's data cache was reloaded from a localtion other than the local core's L2 due to a demand load",
36959826caSMatt Macy    "PublicDescription": "The processor's data cache was reloaded from a localtion other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
37959826caSMatt Macy  },
38*3a3deb00SEd Maste  {
39959826caSMatt Macy    "EventCode": "0x3c040",
40959826caSMatt Macy    "EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST",
41959826caSMatt Macy    "BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load",
42959826caSMatt Macy    "PublicDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
43959826caSMatt Macy  },
44*3a3deb00SEd Maste  {
45959826caSMatt Macy    "EventCode": "0x4c040",
46959826caSMatt Macy    "EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER",
47959826caSMatt Macy    "BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load",
48959826caSMatt Macy    "PublicDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
49959826caSMatt Macy  },
50*3a3deb00SEd Maste  {
51959826caSMatt Macy    "EventCode": "0x2c040",
52959826caSMatt Macy    "EventName": "PM_DATA_FROM_L2_MEPF",
53959826caSMatt Macy    "BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load",
54959826caSMatt Macy    "PublicDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
55959826caSMatt Macy  },
56*3a3deb00SEd Maste  {
57959826caSMatt Macy    "EventCode": "0x1c040",
58959826caSMatt Macy    "EventName": "PM_DATA_FROM_L2_NO_CONFLICT",
59959826caSMatt Macy    "BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load",
60959826caSMatt Macy    "PublicDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
61959826caSMatt Macy  },
62*3a3deb00SEd Maste  {
63959826caSMatt Macy    "EventCode": "0x4c042",
64959826caSMatt Macy    "EventName": "PM_DATA_FROM_L3",
65959826caSMatt Macy    "BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand load",
66959826caSMatt Macy    "PublicDescription": "The processor's data cache was reloaded from local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
67959826caSMatt Macy  },
68*3a3deb00SEd Maste  {
69959826caSMatt Macy    "EventCode": "0x300fe",
70959826caSMatt Macy    "EventName": "PM_DATA_FROM_L3MISS",
71959826caSMatt Macy    "BriefDescription": "Demand LD - L3 Miss (not L2 hit and not L3 hit)",
72959826caSMatt Macy    "PublicDescription": ""
73959826caSMatt Macy  },
74*3a3deb00SEd Maste  {
75959826caSMatt Macy    "EventCode": "0x4c04e",
76959826caSMatt Macy    "EventName": "PM_DATA_FROM_L3MISS_MOD",
77959826caSMatt Macy    "BriefDescription": "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a demand load",
78959826caSMatt Macy    "PublicDescription": "The processor's data cache was reloaded from a localtion other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
79959826caSMatt Macy  },
80*3a3deb00SEd Maste  {
81959826caSMatt Macy    "EventCode": "0x3c042",
82959826caSMatt Macy    "EventName": "PM_DATA_FROM_L3_DISP_CONFLICT",
83959826caSMatt Macy    "BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load",
84959826caSMatt Macy    "PublicDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
85959826caSMatt Macy  },
86*3a3deb00SEd Maste  {
87959826caSMatt Macy    "EventCode": "0x2c042",
88959826caSMatt Macy    "EventName": "PM_DATA_FROM_L3_MEPF",
89959826caSMatt Macy    "BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load",
90959826caSMatt Macy    "PublicDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
91959826caSMatt Macy  },
92*3a3deb00SEd Maste  {
93959826caSMatt Macy    "EventCode": "0x1c044",
94959826caSMatt Macy    "EventName": "PM_DATA_FROM_L3_NO_CONFLICT",
95959826caSMatt Macy    "BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load",
96959826caSMatt Macy    "PublicDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
97959826caSMatt Macy  },
98*3a3deb00SEd Maste  {
99959826caSMatt Macy    "EventCode": "0x1c04c",
100959826caSMatt Macy    "EventName": "PM_DATA_FROM_LL4",
101959826caSMatt Macy    "BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to a demand load",
102959826caSMatt Macy    "PublicDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
103959826caSMatt Macy  },
104*3a3deb00SEd Maste  {
105959826caSMatt Macy    "EventCode": "0x4c04a",
106959826caSMatt Macy    "EventName": "PM_DATA_FROM_OFF_CHIP_CACHE",
107959826caSMatt Macy    "BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a demand load",
108959826caSMatt Macy    "PublicDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
109959826caSMatt Macy  },
110*3a3deb00SEd Maste  {
111959826caSMatt Macy    "EventCode": "0x1c048",
112959826caSMatt Macy    "EventName": "PM_DATA_FROM_ON_CHIP_CACHE",
113959826caSMatt Macy    "BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a demand load",
114959826caSMatt Macy    "PublicDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
115959826caSMatt Macy  },
116*3a3deb00SEd Maste  {
117959826caSMatt Macy    "EventCode": "0x2c046",
118959826caSMatt Macy    "EventName": "PM_DATA_FROM_RL2L3_MOD",
119959826caSMatt Macy    "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load",
120959826caSMatt Macy    "PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
121959826caSMatt Macy  },
122*3a3deb00SEd Maste  {
123959826caSMatt Macy    "EventCode": "0x1c04a",
124959826caSMatt Macy    "EventName": "PM_DATA_FROM_RL2L3_SHR",
125959826caSMatt Macy    "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load",
126959826caSMatt Macy    "PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
127959826caSMatt Macy  },
128*3a3deb00SEd Maste  {
129959826caSMatt Macy    "EventCode": "0x3001a",
130959826caSMatt Macy    "EventName": "PM_DATA_TABLEWALK_CYC",
131959826caSMatt Macy    "BriefDescription": "Tablwalk Cycles (could be 1 or 2 active)",
132959826caSMatt Macy    "PublicDescription": "Data Tablewalk Active"
133959826caSMatt Macy  },
134*3a3deb00SEd Maste  {
135959826caSMatt Macy    "EventCode": "0x4e04e",
136959826caSMatt Macy    "EventName": "PM_DPTEG_FROM_L3MISS",
137959826caSMatt Macy    "BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a data side request",
138959826caSMatt Macy    "PublicDescription": ""
139959826caSMatt Macy  },
140*3a3deb00SEd Maste  {
141959826caSMatt Macy    "EventCode": "0xd094",
142959826caSMatt Macy    "EventName": "PM_DSLB_MISS",
143959826caSMatt Macy    "BriefDescription": "Data SLB Miss - Total of all segment sizes",
144959826caSMatt Macy    "PublicDescription": "Data SLB Miss - Total of all segment sizesData SLB misses"
145959826caSMatt Macy  },
146*3a3deb00SEd Maste  {
147959826caSMatt Macy    "EventCode": "0x1002c",
148959826caSMatt Macy    "EventName": "PM_L1_DCACHE_RELOADED_ALL",
149959826caSMatt Macy    "BriefDescription": "L1 data cache reloaded for demand or prefetch",
150959826caSMatt Macy    "PublicDescription": ""
151959826caSMatt Macy  },
152*3a3deb00SEd Maste  {
153959826caSMatt Macy    "EventCode": "0x300f6",
154959826caSMatt Macy    "EventName": "PM_L1_DCACHE_RELOAD_VALID",
155959826caSMatt Macy    "BriefDescription": "DL1 reloaded due to Demand Load",
156959826caSMatt Macy    "PublicDescription": ""
157959826caSMatt Macy  },
158*3a3deb00SEd Maste  {
159959826caSMatt Macy    "EventCode": "0x3e054",
160959826caSMatt Macy    "EventName": "PM_LD_MISS_L1",
161959826caSMatt Macy    "BriefDescription": "Load Missed L1",
162959826caSMatt Macy    "PublicDescription": ""
163959826caSMatt Macy  },
164*3a3deb00SEd Maste  {
165959826caSMatt Macy    "EventCode": "0x100ee",
166959826caSMatt Macy    "EventName": "PM_LD_REF_L1",
167959826caSMatt Macy    "BriefDescription": "All L1 D cache load references counted at finish, gated by reject",
168959826caSMatt Macy    "PublicDescription": "Load Ref count combined for all units"
169959826caSMatt Macy  },
170*3a3deb00SEd Maste  {
171959826caSMatt Macy    "EventCode": "0x300f0",
172959826caSMatt Macy    "EventName": "PM_ST_MISS_L1",
173959826caSMatt Macy    "BriefDescription": "Store Missed L1",
174959826caSMatt Macy    "PublicDescription": ""
175*3a3deb00SEd Maste  }
176959826caSMatt Macy]
177