Lines Matching +full:l2 +full:- +full:cache

45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
61 .%N "Order Number: 325462-045US"
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
89 Configure the Off-core Response bits.
90 .Bl -tag -width indent
95 Does not count L2 data read prefetches or instruction fetches.
99 Does not count L2 RFO prefetches.
102 Does not count L2 code read prefetches.
106 Counts the number of data cacheline reads generated by L2 prefetchers.
108 Counts the number of RFO requests generated by L2 prefetchers.
110 Counts the number of code reads generated by L2 prefetchers.
112 L2 prefetcher to L3 for loads.
114 RFO requests generated by L2 prefetcher
116 L2 prefetcher to L3 for instruction fetches.
128 M-state initial lookup stat in L3.
130 E-state.
132 S-state.
134 F-state.
138 No details on snoop-related information.
147 A snoop was needed and it hits in at least one snooped cache.
148 Hit denotes a cache-line was valid before snoop effect.
159 A snoop was needed and it HitM-ed in local or remote cache.
160 HitM denotes a cache-line was in modified state before effect as a results of snoop.
166 Target was non-DRAM system address.
174 Configure the PMC to count the number of de-asserted to asserted
201 .Bl -tag -width indent
208 Speculative cache-line split load uops dispatched to
212 Speculative cache-line split Store-address uops
245 Number of cache load STLB hits.
249 DTLB demand load misses with low part of linear-to-
264 Number of flags-merge uops allocated.
277 Demand Data Read requests that missed L2, no
281 Demand Data Read requests that hit L2 cache.
285 requests to L2.
289 the L2 cache.
293 the L2 cache.
296 Counts all L2 store RFO requests.
299 Number of instruction fetches that hit the L2 cache.
302 Number of instruction fetches that missed the L2
303 cache.
306 Demand requests that miss L2 cache.
309 Demand requests to L2 cache.
312 Counts all L2 code requests.
315 Counts all L2 HW prefetcher requests that hit L2.
318 Counts all L2 HW prefetcher requests that missed
319 L2.
322 Counts all L2 HW prefetcher requests.
325 All requests that missed L2.
328 All requests to L2 cache.
331 Not rejected writebacks that hit L2 cache
335 that reference a cache line in the last level cache.
338 This event counts each cache miss condition for
339 references to the last level cache.
384 DTLB store misses with low part of linear-to-physical
388 Non-SW-prefetch load dispatches that hit fill buffer
392 Non-SW-prefetch load dispatches that hit fill buffer
397 cache.
440 Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.
490 Number of Instruction Cache, Streaming Buffer and Victim Cache Misses.
583 Count number of non-delivered uops to RAT per
630 Cycles stalled due to re-order buffer full.
633 Cycles with pending L2 miss loads.
641 Number of loads missed L2.
644 Cycles with pending L1 cache miss loads.
666 Counts total number of uops to be executed per-core
684 Number of DTLB page walker loads that hit in the L2.
687 Number of ITLB page walker loads that hit in the L2.
702 DTLB flush attempts of the thread-specific entries.
715 Number of transitions from AVX-256 to legacy SSE
719 Number of transitions from SSE to AVX-256 when
727 Counts the number of micro-ops retired, Use
740 Number of self-modifying-code machine clears
813 Count retired load uops that were split across a cache line.
816 Count retired store uops that were split across a cache line.
825 Retired load uops with L1 cache hits as data sources.
828 Retired load uops with L2 cache hits as data sources.
831 Retired load uops with LLC cache hits as data
835 Retired load uops missed L2.
841 same cache line with data not ready.
845 and cross-core snoop missed in on-pkg core cache.
849 cross-core snoop hits in on-pkg core cache.
864 Number of front end re-steers due to BPU
868 Demand Data Read requests that access L2 cache.
871 RFO requests that access L2 cache.
874 L2 cache accesses when fetching instructions.
877 Any MLC or LLC HW prefetch accessing L2, including
881 L1D writebacks that access L2 cache.
884 L2 fill requests that access L2 cache.
887 L2 writebacks that access L2 cache.
890 Transactions accessing L2 pipe.
893 L2 cache lines in I state filling L2.
896 L2 cache lines in S state filling L2.
899 L2 cache lines in E state filling L2.
902 L2 cache lines filling L2.
905 Clean L2 cache lines evicted by demand.
908 Dirty L2 cache lines evicted by demand.
938 .An -nosplit