| /linux/drivers/counter/ |
| H A D | interrupt-cnt.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/irq.h>
17 #define INTERRUPT_CNT_NAME "interrupt-cnt"
22 int irq; member
25 struct counter_signal signals; member
30 static irqreturn_t interrupt_cnt_isr(int irq, void *dev_id) in interrupt_cnt_isr() argument
35 atomic_long_inc(&priv->count); in interrupt_cnt_isr()
47 guard(mutex)(&priv->lock); in interrupt_cnt_enable_read()
49 *enable = priv->enabled; in interrupt_cnt_enable_read()
59 guard(mutex)(&priv->lock); in interrupt_cnt_enable_write()
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| /linux/arch/um/os-Linux/ |
| H A D | signal.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 Anton Ivanov (aivanov@{brocade.com,kot-begemot.co.uk})
6 * Copyright (C) 2004 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
16 #include <as-layout.h>
47 /* enable signals if sig isn't IRQ signal */ in sig_handler_common()
57 * These are the asynchronous signals. SIGPROF is excluded because we want to
58 * be able to profile all of UML, not just the non-critical sections. If
59 * profiling is not thread-safe, then that is not my problem. We can disable
95 * In TT_MODE_EXTERNAL, need to still call time-travel in sig_handler()
98 * Note we won't get here if signals are hard-blocked in sig_handler()
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| /linux/drivers/tty/ |
| H A D | synclink_gt.c | 1 // SPDX-License-Identifier: GPL-1.0+
28 * DBGINFO information - most verbose output
76 #include <asm/irq.h>
146 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
252 bool irq_requested; /* true if IRQ requested */
284 unsigned char signals; /* serial signal states */ member
496 printk("%s %s data:\n",info->device_name, label); in trace_block()
511 count -= linecount; in trace_block()
522 printk("tbuf_current=%d\n", info->tbuf_current); in dump_tbufs()
523 for (i=0 ; i < info->tbuf_count ; i++) { in dump_tbufs()
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| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_hw_fence_types.h | 1 /* SPDX-License-Identifier: MIT */
9 #include <linux/dma-fence.h>
10 #include <linux/iosys-map.h>
19 * struct xe_hw_fence_irq - hardware fence IRQ handler
21 * One per engine class, signals completed xe_hw_fences, triggered via hw engine
27 /** @work: IRQ worker run to signal the fences */
38 * struct xe_hw_fence_ctx - hardware fence context
46 /** @irq: fence irq handler */
47 struct xe_hw_fence_irq *irq; member
57 * struct xe_hw_fence - hardware fence
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| H A D | xe_range_fence.h | 1 /* SPDX-License-Identifier: MIT */
9 #include <linux/dma-fence.h>
16 /** struct xe_range_fence_ops - XE range fence ops */
22 /** struct xe_range_fence - XE range fence (address conflict tracking) */
33 * @fence: fence signals address in range fence no longer has conflict
39 * @cb: callback when fence signals to remove range fence free from interval tree
42 /** @link: used to defer free of range fence to non-irq context */
48 /** struct xe_range_fence_tree - interval tree to store range fences */
|
| /linux/Documentation/driver-api/gpio/ |
| H A D | intro.rst | 17 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
25 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
26 non-dedicated pin can be configured as a GPIO; and most chips have at least
31 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
36 - Output values are writable (high=1, low=0). Some chips also have
38 value might be driven, supporting "wire-OR" and similar schemes for the
41 - Input values are likewise readable (1, 0). Some chips support readback
42 of pins configured as "output", which is very useful in such "wire-OR"
44 input de-glitch/debounce logic, sometimes with software controls.
46 - Inputs can often be used as IRQ signals, often edge triggered but
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | snps,dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
25 and is split up into several sub-parts Standard PCIe configuration
26 space, Port Logic Registers (PL), Shadow Config-space Registers,
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| H A D | snps,dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
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| H A D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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| /linux/drivers/gpio/ |
| H A D | gpio-eic-sprd.c | 1 // SPDX-License-Identifier: GPL-2.0
54 * The digital-chip EIC controller can support maximum 3 banks, and each bank
60 #define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1))
65 * input mode to generate interrupts if detecting input signals.
67 * The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
70 * The debounce EIC is used to capture the input signals' stable status
71 * (millisecond resolution) and a single-trigger mechanism is introduced
72 * into this sub-module to enhance the input event detection reliability.
75 * The latch EIC is used to latch some special power down signals and
77 * to capture signals.
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| H A D | gpio-xilinx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2008 - 2013 Xilinx, Inc.
16 #include <linux/irq.h>
45 * struct xgpio_instance - Stores information about GPIO device
53 * @irq: IRQ used by GPIO device
54 * @enable: GPIO IRQ enable/disable bitfield
55 * @rising_edge: GPIO IRQ rising edge enable/disable bitfield
56 * @falling_edge: GPIO IRQ falling edge enable/disable bitfield
67 int irq; member
82 return -EINVAL; in xgpio_regoffset()
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| /linux/drivers/irqchip/ |
| H A D | irq-mtk-cirq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/irq.h>
71 return chip_data->base + chip_data->offsets[idx]; in mtk_cirq_reg()
83 struct mtk_cirq_chip_data *chip_data = data->chip_data; in mtk_cirq_write_mask()
84 unsigned int cirq_num = data->hwirq; in mtk_cirq_write_mask()
127 data = data->parent_data; in mtk_cirq_set_type()
128 ret = data->chip->irq_set_type(data, type); in mtk_cirq_set_type()
149 if (is_of_node(fwspec->fwnode)) { in mtk_cirq_domain_translate()
150 if (fwspec->param_count != 3) in mtk_cirq_domain_translate()
151 return -EINVAL; in mtk_cirq_domain_translate()
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | microchip,sparx5-sgpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
16 connect control signals from SFP modules and to act as an LED
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
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| /linux/arch/m68k/mac/ |
| H A D | macints.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * exclusively use the autovector interrupts (the 'generic level0-level7'
8 * interrupts with exception vectors 0x19-0x1f). The following interrupt levels
10 * 1 - VIA1
11 * - slot 0: one second interrupt (CA2)
12 * - slot 1: VBlank (CA1)
13 * - slot 2: ADB data ready (SR full)
14 * - slot 3: ADB data (CB2)
15 * - slot 4: ADB clock (CB1)
16 * - slot 5: timer 2
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| /linux/drivers/platform/mellanox/ |
| H A D | mlxreg-hotplug.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2016-2020 Mellanox Technologies
11 #include <linux/hwmon-sysfs.h>
34 * struct mlxreg_hotplug_priv_data - platform private data:
35 * @irq: platform device interrupt number;
54 int irq; member
85 string_upper(label, data->label); in mlxreg_hotplug_udev_event_send()
97 dev_pdata->regmap = regmap; in mlxreg_hotplug_pdata_export()
104 struct i2c_board_info *brdinfo = data->hpdev.brdinfo; in mlxreg_hotplug_device_create()
109 mlxreg_hotplug_udev_event_send(&priv->hwmon->kobj, data, true); in mlxreg_hotplug_device_create()
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| /linux/drivers/parisc/ |
| H A D | iosapic_private.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Copyright (C) 2000,2003 Grant Grundler (grundler at parisc-linux.org)
7 * Copyright (C) 2002 Matthew Wilcox (willy at parisc-linux.org)
15 ** they pack nicely for 64-bit compilation. (ie sizeof(long) == 8)
21 ** -----------------------
24 ** table per cell. N- and L-class consist of a single cell.
42 ** Polarity of SAPIC I/O input signals:
47 ** Trigger mode of SAPIC I/O input signals:
49 ** 01 = Edge-triggered
51 ** 11 = Level-triggered
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| /linux/Documentation/power/ |
| H A D | suspend-and-interrupts.rst | 10 -----------------------------------
14 ->prepare, ->suspend and ->suspend_late callbacks have been executed for all
29 Device IRQs are re-enabled during system resume, right before the "early" phase
30 of resuming devices (that is, before starting to execute ->resume_early
35 ------------------------
38 suspend-resume cycle, including the "noirq" phases of suspending and resuming
41 but also to IPIs and to some other special-purpose interrupts.
43 The IRQF_NO_SUSPEND flag is used to indicate that to the IRQ subsystem when
44 requesting a special-purpose interrupt. It causes suspend_device_irqs() to
45 leave the corresponding IRQ enabled so as to allow the interrupt to work as
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|
| /linux/include/linux/ |
| H A D | lp.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * usr/include/linux/lp.h c.1991-1992 James Wiegand
16 /* Magic numbers for defining port-device mappings */
17 #define LP_PARPORT_UNSPEC -4
18 #define LP_PARPORT_AUTO -3
19 #define LP_PARPORT_OFF -2
20 #define LP_PARPORT_NONE -1
26 #define LP_IRQ(minor) lp_table[(minor)].dev->port->irq /* interrupt # */
33 #define LP_BASE(x) lp_table[(x)].dev->port->base
69 * The following constants describe the various signals of the printer port
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | ti,keystone-irq.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ti,keystone-irq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Keystone 2 IRQ controller IP
10 - Grygorii Strashko <grygorii.strashko@ti.com>
13 On Keystone SOCs, DSP cores can send interrupts to ARM host using the IRQ
14 controller IP. It provides 28 IRQ signals to ARM. The IRQ handler running on
21 const: ti,keystone-irq
26 interrupt-controller: true
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| H A D | ti,omap-intc-irq.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,omap-intc-irq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
13 On TI omap2 and 3 the intc interrupt controller can provide 96 or 128 IRQ
14 signals to the ARM host depending on the SoC.
19 - ti,omap2-intc
20 - ti,omap3-intc
21 - ti,dm814-intc
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| /linux/include/soc/at91/ |
| H A D | atmel_tcb.h | 17 * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
18 * three general-purpose 16-bit timers. These timers share one register bank.
19 * Depending on the SOC, each timer may have its own clock and IRQ, or those
22 * These TC blocks may have up to nine external pins: TCLK0..2 signals for
23 * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
31 * IRQ resources.
37 * struct atmel_tcb_config - SoC data for a Timer/Counter Block
50 * struct atmel_tc - information about a Timer/Counter Block
55 * @irq: irq for each of the three channels
61 * while on others, all TC channels share the same clock and IRQ.
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| /linux/Documentation/devicetree/bindings/input/ |
| H A D | goodix,gt7375p.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Douglas Anderson <dianders@chromium.org>
14 This touchscreen uses the i2c-hid protocol but has some non-standard
18 - $ref: /schemas/input/touchscreen/touchscreen.yaml#
23 - const: goodix,gt7375p
24 - items:
25 - const: goodix,gt7986u
26 - const: goodix,gt7375p
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| /linux/drivers/comedi/drivers/ |
| H A D | addi_apci_1500.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
6 * ADDI-DATA GmbH
8 * D-77833 Ottersweier
9 * Tel: +19(0)7223/9493-0
10 * Fax: +49(0)7223/9493-92
11 * http://www.addi-data.com
12 * info@addi-data.com
23 * PCI Bar 0 Register map (devpriv->amcc)
28 * PCI Bar 1 Register map (dev->iobase)
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| /linux/arch/microblaze/kernel/ |
| H A D | entry.S | 2 * Low-level system-call handling, trap handlers and context-switching
4 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
5 * Copyright (C) 2008-2009 PetaLogix
25 #include <asm/asm-offsets.h>
160 /* Define how to call high-level functions. With MMU, virtual mode must be
161 * enabled when calling the high-level function. Clobbers R11.
192 swi r14, r1, PT_PC; /* PC, before IRQ/trap */ \
226 lwi r14, r1, PT_PC; /* RESTORE_LINK PC, before IRQ/trap */\
263 /* Kernel-mode state save. */ \
264 /* Reload kernel stack-ptr. */ \
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| /linux/Documentation/devicetree/bindings/gpio/ |
| H A D | ti,keystone-dsp-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/ti,keystone-dsp-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Grygorii Strashko <grygorii.strashko@ti.com>
14 the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
18 - 8 for C66x CorePacx CPUs 0-7
21 - each GPIO can be configured only as output pin;
22 - setting GPIO value to 1 causes IRQ generation on target DSP core;
23 - reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
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